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Align req and rsp types to #153
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@micprog
micprog committed Jan 20, 2022
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2 changes: 1 addition & 1 deletion doc/axi_lite_mailbox.md
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Expand Up @@ -16,7 +16,7 @@ This table describes the parameters of the module.
| `AxiAddrWidth` | `int unsigned` | The AXI4-Lite address width on the AW and AR channels |
| `AxiDataWidth` | `int unsigned` | The AXI4-Lite data width on the W and R channels |
| `req_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_REQ_T` macro |
| `resp_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_RESP_T` macro |
| `rsp_lite_t` | `type` | In accordance with the `AXI_LITE_TYPEDEF_RSP_T` macro |


## Module Ports
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2 changes: 1 addition & 1 deletion doc/axi_lite_xbar.md
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Expand Up @@ -40,7 +40,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
| `AxiDataWidth` | `int unsigned` | The AXI4-Lite data width. |
| `NoAddrRules` | `int unsigned` | The number of address map rules. |

The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_resp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.

### Pipelining and Latency

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2 changes: 1 addition & 1 deletion doc/axi_xbar.md
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Expand Up @@ -54,7 +54,7 @@ The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg
| `AxiDataWidth` | `int unsigned` | The AXI data width. |
| `NoAddrRules` | `int unsigned` | The number of address map rules. |

The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_resp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.
The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_rsp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses.

### Pipelining and Latency

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20 changes: 10 additions & 10 deletions include/axi/typedef.svh
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Expand Up @@ -29,7 +29,7 @@
// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t)
// `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t)
// `AXI_TYPEDEF_RSP_T(axi_rsp_t, axi_b_t, axi_r_t)
`define AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) \
typedef struct packed { \
id_t id; \
Expand Down Expand Up @@ -91,7 +91,7 @@
logic ar_valid; \
logic r_ready; \
} req_t;
`define AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t) \
`define AXI_TYPEDEF_RSP_T(rsp_t, b_chan_t, r_chan_t) \
typedef struct packed { \
logic aw_ready; \
logic ar_ready; \
Expand All @@ -100,7 +100,7 @@
b_chan_t b; \
logic r_valid; \
r_chan_t r; \
} resp_t;
} rsp_t;
////////////////////////////////////////////////////////////////////////////////////////////////////


Expand All @@ -113,7 +113,7 @@
// Usage Example:
// `AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t)
//
// This defines `axi_req_t` and `axi_resp_t` request/response structs as well as `axi_aw_chan_t`,
// This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`,
// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs.
`define AXI_TYPEDEF_ALL(__name, __addr_t, __id_t, __data_t, __strb_t, __user_t) \
`AXI_TYPEDEF_AW_CHAN_T(__name``_aw_chan_t, __addr_t, __id_t, __user_t) \
Expand All @@ -122,7 +122,7 @@
`AXI_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t, __id_t, __user_t) \
`AXI_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t, __id_t, __user_t) \
`AXI_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \
`AXI_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t)
`AXI_TYPEDEF_RSP_T(__name``_rsp_t, __name``_b_chan_t, __name``_r_chan_t)
////////////////////////////////////////////////////////////////////////////////////////////////////


Expand All @@ -136,7 +136,7 @@
// `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t)
// `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_r_t, axi_lite_data_t)
// `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t)
// `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t)
// `AXI_LITE_TYPEDEF_RSP_T(axi_lite_rsp_t, axi_lite_b_t, axi_lite_r_t)
`define AXI_LITE_TYPEDEF_AW_CHAN_T(aw_chan_lite_t, addr_t) \
typedef struct packed { \
addr_t addr; \
Expand Down Expand Up @@ -172,7 +172,7 @@
logic ar_valid; \
logic r_ready; \
} req_lite_t;
`define AXI_LITE_TYPEDEF_RESP_T(resp_lite_t, b_chan_lite_t, r_chan_lite_t) \
`define AXI_LITE_TYPEDEF_RSP_T(rsp_lite_t, b_chan_lite_t, r_chan_lite_t) \
typedef struct packed { \
logic aw_ready; \
logic w_ready; \
Expand All @@ -181,7 +181,7 @@
logic ar_ready; \
r_chan_lite_t r; \
logic r_valid; \
} resp_lite_t;
} rsp_lite_t;
////////////////////////////////////////////////////////////////////////////////////////////////////


Expand All @@ -194,7 +194,7 @@
// Usage Example:
// `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t)
//
// This defines `axi_lite_req_t` and `axi_lite_resp_t` request/response structs as well as
// This defines `axi_lite_req_t` and `axi_lite_rsp_t` request/response structs as well as
// `axi_lite_aw_chan_t`, `axi_lite_w_chan_t`, `axi_lite_b_chan_t`, `axi_lite_ar_chan_t`, and
// `axi_lite_r_chan_t` channel structs.
`define AXI_LITE_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t) \
Expand All @@ -204,7 +204,7 @@
`AXI_LITE_TYPEDEF_AR_CHAN_T(__name``_ar_chan_t, __addr_t) \
`AXI_LITE_TYPEDEF_R_CHAN_T(__name``_r_chan_t, __data_t) \
`AXI_LITE_TYPEDEF_REQ_T(__name``_req_t, __name``_aw_chan_t, __name``_w_chan_t, __name``_ar_chan_t) \
`AXI_LITE_TYPEDEF_RESP_T(__name``_resp_t, __name``_b_chan_t, __name``_r_chan_t)
`AXI_LITE_TYPEDEF_RSP_T(__name``_rsp_t, __name``_b_chan_t, __name``_r_chan_t)
////////////////////////////////////////////////////////////////////////////////////////////////////


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48 changes: 24 additions & 24 deletions scripts/axi_intercon_gen.py
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Expand Up @@ -377,10 +377,10 @@ def write(self):
`AXI_TYPEDEF_R_CHAN_T(r_chan_mst_t, data_t, id_mst_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t)
`AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t)
`AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_mst_t, r_chan_mst_t)
`AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t)
`AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_slv_t, r_chan_slv_t)
`AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t)
`AXI_TYPEDEF_RSP_T(slv_port_axi_rsp_t, b_chan_mst_t, r_chan_mst_t)
`AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t)
`AXI_TYPEDEF_RSP_T(mst_port_axi_rsp_t, b_chan_slv_t, r_chan_slv_t)
"""

Expand All @@ -397,34 +397,34 @@ def write(self):
raw += ',\n'.join(rules)
raw += "};\n"

raw += " slv_req_t [{}:0] masters_req;\n".format(nm-1)
raw += " slv_resp_t [{}:0] masters_resp;\n".format(nm-1)
raw += " slv_port_axi_req_t [{}:0] masters_req;\n".format(nm-1)
raw += " slv_port_axi_rsp_t [{}:0] masters_resp;\n".format(nm-1)

raw += " mst_req_t [{}:0] slaves_req;\n".format(ns-1)
raw += " mst_resp_t [{}:0] slaves_resp;\n".format(ns-1)
raw += " mst_port_axi_req_t [{}:0] slaves_req;\n".format(ns-1)
raw += " mst_port_axi_rsp_t [{}:0] slaves_resp;\n".format(ns-1)

ns = len(self.slaves)

raw += assigns(w, max_idw, self.masters, self.slaves)

self.verilog_writer.raw = raw
parameters = [
Parameter('Cfg' , 'xbar_cfg' ),
Parameter('ATOPs' , "1'b"+str(int(self.atop))),
Parameter('slv_aw_chan_t', 'aw_chan_mst_t'),
Parameter('mst_aw_chan_t', 'aw_chan_slv_t'),
Parameter('w_chan_t' , 'w_chan_t' ),
Parameter('slv_b_chan_t' , 'b_chan_mst_t' ),
Parameter('mst_b_chan_t' , 'b_chan_slv_t' ),
Parameter('slv_ar_chan_t', 'ar_chan_mst_t'),
Parameter('mst_ar_chan_t', 'ar_chan_slv_t'),
Parameter('slv_r_chan_t' , 'r_chan_mst_t' ),
Parameter('mst_r_chan_t' , 'r_chan_slv_t' ),
Parameter('slv_req_t' , 'slv_req_t' ),
Parameter('slv_resp_t' , 'slv_resp_t' ),
Parameter('mst_req_t' , 'mst_req_t' ),
Parameter('mst_resp_t' , 'mst_resp_t' ),
Parameter('rule_t' , 'rule_t' ),
Parameter('Cfg' , 'xbar_cfg' ),
Parameter('ATOPs' , "1'b"+str(int(self.atop))),
Parameter('slv_aw_chan_t' , 'aw_chan_mst_t' ),
Parameter('mst_aw_chan_t' , 'aw_chan_slv_t' ),
Parameter('w_chan_t' , 'w_chan_t' ),
Parameter('slv_b_chan_t' , 'b_chan_mst_t' ),
Parameter('mst_b_chan_t' , 'b_chan_slv_t' ),
Parameter('slv_ar_chan_t' , 'ar_chan_mst_t' ),
Parameter('mst_ar_chan_t' , 'ar_chan_slv_t' ),
Parameter('slv_r_chan_t' , 'r_chan_mst_t' ),
Parameter('mst_r_chan_t' , 'r_chan_slv_t' ),
Parameter('slv_port_axi_req_t', 'slv_port_axi_req_t' ),
Parameter('slv_port_axi_rsp_t', 'slv_port_axi_rsp_t' ),
Parameter('mst_port_axi_req_t', 'mst_port_axi_req_t' ),
Parameter('mst_port_axi_rsp_t', 'mst_port_axi_rsp_t' ),
Parameter('rule_t' , 'rule_t' ),
]
ports = instance_ports(w, max_idw, self.masters, self.slaves)

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22 changes: 11 additions & 11 deletions src/axi_atop_filter.sv
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Expand Up @@ -40,22 +40,22 @@ module axi_atop_filter #(
/// Maximum number of in-flight AXI write transactions
parameter int unsigned AxiMaxWriteTxns = 0,
/// AXI request type
parameter type axi_req_t = logic,
parameter type axi_req_t = logic,
/// AXI response type
parameter type axi_resp_t = logic
parameter type axi_rsp_t = logic
) (
/// Rising-edge clock of both ports
input logic clk_i,
input logic clk_i,
/// Asynchronous reset, active low
input logic rst_ni,
input logic rst_ni,
/// Slave port request
input axi_req_t slv_req_i,
input axi_req_t slv_req_i,
/// Slave port response
output axi_resp_t slv_resp_o,
output axi_rsp_t slv_resp_o,
/// Master port request
output axi_req_t mst_req_o,
output axi_req_t mst_req_o,
/// Master port response
input axi_resp_t mst_resp_i
input axi_rsp_t mst_resp_i
);

// Minimum counter width is 2 to detect underflows.
Expand Down Expand Up @@ -406,10 +406,10 @@ module axi_atop_filter_intf #(
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
`AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t)
`AXI_TYPEDEF_RESP_T(axi_resp_t, b_chan_t, r_chan_t)
`AXI_TYPEDEF_RSP_T(axi_rsp_t, b_chan_t, r_chan_t)

axi_req_t slv_req, mst_req;
axi_resp_t slv_resp, mst_resp;
axi_rsp_t slv_resp, mst_resp;

`AXI_ASSIGN_TO_REQ(slv_req, slv)
`AXI_ASSIGN_FROM_RESP(slv, slv_resp)
Expand All @@ -423,7 +423,7 @@ module axi_atop_filter_intf #(
.AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ),
// AXI request & response type
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t )
.axi_rsp_t ( axi_rsp_t )
) i_axi_atop_filter (
.clk_i,
.rst_ni,
Expand Down
22 changes: 11 additions & 11 deletions src/axi_burst_splitter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -36,18 +36,18 @@ module axi_burst_splitter #(
parameter int unsigned IdWidth = 32'd0,
parameter int unsigned UserWidth = 32'd0,
parameter type axi_req_t = logic,
parameter type axi_resp_t = logic
parameter type axi_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
input logic clk_i,
input logic rst_ni,

// Input / Slave Port
input axi_req_t slv_req_i,
output axi_resp_t slv_resp_o,
input axi_req_t slv_req_i,
output axi_rsp_t slv_resp_o,

// Output / Master Port
output axi_req_t mst_req_o,
input axi_resp_t mst_resp_i
output axi_req_t mst_req_o,
input axi_rsp_t mst_resp_i
);

typedef logic [AddrWidth-1:0] addr_t;
Expand All @@ -62,8 +62,8 @@ module axi_burst_splitter #(
`AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)

// Demultiplex between supported and unsupported transactions.
axi_req_t act_req, unsupported_req;
axi_resp_t act_resp, unsupported_resp;
axi_req_t act_req, unsupported_req;
axi_rsp_t act_resp, unsupported_resp;
logic sel_aw_unsupported, sel_ar_unsupported;
localparam int unsigned MaxTxns = (MaxReadTxns > MaxWriteTxns) ? MaxReadTxns : MaxWriteTxns;
axi_demux #(
Expand All @@ -74,7 +74,7 @@ module axi_burst_splitter #(
.ar_chan_t ( ar_chan_t ),
.r_chan_t ( r_chan_t ),
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.axi_rsp_t ( axi_rsp_t ),
.NoMstPorts ( 2 ),
.MaxTrans ( MaxTxns ),
.AxiLookBits ( IdWidth ),
Expand Down Expand Up @@ -120,7 +120,7 @@ module axi_burst_splitter #(
axi_err_slv #(
.AxiIdWidth ( IdWidth ),
.axi_req_t ( axi_req_t ),
.axi_resp_t ( axi_resp_t ),
.axi_rsp_t ( axi_rsp_t ),
.Resp ( axi_pkg::RESP_SLVERR ),
.ATOPs ( 1'b0 ), // The burst splitter does not support ATOPs.
.MaxTrans ( 1 ) // Splitting bursts implies a low-performance bus.
Expand Down
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