[LA64_DYNAREC] Added more opcodes (#2215)

ptitSeb · Dec 26, 2024 · cd1ac51 · cd1ac51
1 parent a7ded59
commit cd1ac51
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Showing 4 changed files with 45 additions and 6 deletions.
diff --git a/src/dynarec/la64/dynarec_la64_00.c b/src/dynarec/la64/dynarec_la64_00.c
@@ -1610,6 +1610,16 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
             nextop = F8;
             // TODO: refine these...
             switch ((nextop >> 3) & 7) {
+                case 0:
+                    INST_NAME("ROL Eb, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    SETFLAGS(X_OF | X_CF, SF_SET_DF, NAT_FLAGS_NOFUSION);
+                    GETEB(x1, 1);
+                    u8 = F8;
+                    MOV32w(x2, u8);
+                    CALL_(rol8, ed, x3);
+                    EBBACK();
+                    break;
                 case 4:
                 case 6:
                     INST_NAME("SHL Eb, Ib");
@@ -1920,6 +1930,21 @@ uintptr_t dynarec64_00(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ni
         case 0xD2: // TODO: Jump if CL is 0
             nextop = F8;
             switch ((nextop >> 3) & 7) {
+                case 0:
+                    if (opcode == 0xD0) {
+                        INST_NAME("ROL Eb, 1");
+                        GETEB(x1, 0);
+                        MOV32w(x2, 1);
+                    } else {
+                        INST_NAME("ROL Eb, CL");
+                        GETEB(x1, 0);
+                        ANDI(x2, xRCX, 0x1f);
+                    }
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    SETFLAGS(X_OF | X_CF, SF_SET_DF, NAT_FLAGS_NOFUSION);
+                    CALL_(rol8, ed, x3);
+                    EBBACK();
+                    break;
                 case 4:
                 case 6:
                     if (opcode == 0xD0) {

diff --git a/src/dynarec/la64/dynarec_la64_660f.c b/src/dynarec/la64/dynarec_la64_660f.c
@@ -692,19 +692,24 @@ uintptr_t dynarec64_660F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int
                         SMWRITE2();
                     }
                     break;
+                case 0x20:
+                    INST_NAME("PINSRB Gx, ED, Ib");
+                    nextop = F8;
+                    GETGX(q0, 1);
+                    GETED(1);
+                    u8 = F8;
+                    VINSGR2VR_B(q0, ed, (u8 & 0xf));
+                    break;
                 case 0x22:
                     INST_NAME("PINSRD Gx, ED, Ib");
                     nextop = F8;
                     GETGX(q0, 1);
                     GETED(1);
                     u8 = F8;
-                    d0 = fpu_get_scratch(dyn);
                     if (rex.w) {
-                        MOVGR2FR_D(d0, ed);
-                        VEXTRINS_D(q0, d0, (u8 & 1) << 4);
+                        VINSGR2VR_D(q0, ed, (u8 & 1));
                     } else {
-                        MOVGR2FR_W(d0, ed);
-                        VEXTRINS_W(q0, d0, (u8 & 3) << 4);
+                        VINSGR2VR_W(q0, ed, (u8 & 3));
                     }
                     break;
                 case 0x44:

diff --git a/src/dynarec/la64/dynarec_la64_f30f.c b/src/dynarec/la64/dynarec_la64_f30f.c
@@ -80,6 +80,13 @@ uintptr_t dynarec64_F30F(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int
                 SMWRITE2();
             }
             break;
+        case 0x12:
+            INST_NAME("MOVSLDUP Gx, Ex");
+            nextop = F8;
+            GETEX(q1, 0, 0);
+            GETGX_empty(q0);
+            VPICKEV_W(q0, q1, q1);
+            break;
         case 0x1E:
             INST_NAME("NOP / ENDBR32 / ENDBR64");
             nextop = F8;

diff --git a/src/dynarec/la64/la64_emitter.h b/src/dynarec/la64/la64_emitter.h
@@ -1882,8 +1882,10 @@ LSX instruction starts with V, LASX instruction starts with XV.
 #define XVSRLNI_H_W(vd, vj, imm5)    EMIT(type_2RI5(0b01110111010000001, imm5, vj, vd))
 #define XVSRLI_W(vd, vj, imm5)       EMIT(type_2RI5(0b01110111001100001, imm5, vj, vd))
 #define VSETEQZ_V(cd, vj)            EMIT(type_2R(0b0111001010011100100110, vj, cd & 0b111))
-#define VINSGR2VR_D(vd, rj, imm1)    EMIT(type_2RI1(0b011100101110101111110, imm1, rj, vd))
+#define VINSGR2VR_B(vd, rj, imm4)    EMIT(type_2RI4(0b011100101110101110, imm4, rj, vd))
+#define VINSGR2VR_H(vd, rj, imm3)    EMIT(type_2RI3(0b0111001011101011110, imm3, rj, vd))
 #define VINSGR2VR_W(vd, rj, imm2)    EMIT(type_2RI2(0b01110010111010111110, imm2, rj, vd))
+#define VINSGR2VR_D(vd, rj, imm1)    EMIT(type_2RI1(0b011100101110101111110, imm1, rj, vd))
 #define VPCNT_B(vd, vj)              EMIT(type_2R(0b0111001010011100001000, vj, vd))
 #define VPCNT_H(vd, vj)              EMIT(type_2R(0b0111001010011100001001, vj, vd))
 #define VPCNT_W(vd, vj)              EMIT(type_2R(0b0111001010011100001010, vj, vd))