[INTERPRETER] Exposed SSE4a for CPUTYPE=1, implemented all 4 opcodes

ptitSeb · Dec 27, 2024 · 79413a4 · 79413a4
1 parent 80b357d
commit 79413a4
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Showing 4 changed files with 82 additions and 3 deletions.
diff --git a/src/emu/x64run660f.c b/src/emu/x64run660f.c
@@ -19,6 +19,7 @@
 #include "x64trace.h"
 #include "x87emu_private.h"
 #include "box64context.h"
+#include "signals.h"
 #include "bridge.h"
 
 #include "modrm.h"
@@ -1699,6 +1700,38 @@ uintptr_t Run660F(x64emu_t *emu, rex_t rex, uintptr_t addr)
         for (int i=0; i<4; ++i)
             GX->ud[i] = (GX->ud[i]==EX->ud[i])?0xffffffff:0;
         break;
+
+    case 0x78:  /* EXTRQ Ex, ib, ib */
+        // AMD only
+        nextop = F8;
+        if(!box64_cputype || (nextop&0xC0)>>3) {
+            #ifndef TEST_INTERPRETER
+            emit_signal(emu, SIGILL, (void*)R_RIP, 0);
+            #endif
+        } else {
+            GETEX(2);
+            tmp8u = F8&0x3f;
+            tmp8s = F8&0x3f;
+            EX->q[0]>>tmp8u;
+            EX->q[0]&=(1<<(tmp8s+1)-1);
+        }
+        break;
+    case 0x79:  /* EXTRQ Ex, Gx */
+        // AMD only
+        nextop = F8;
+        if(!box64_cputype || !(MODREG)) {
+            #ifndef TEST_INTERPRETER
+            emit_signal(emu, SIGILL, (void*)R_RIP, 0);
+            #endif
+        } else {
+            GETGX;
+            GETEX(2);
+            tmp8u = GX->ub[0]&0x3f;
+            tmp8s = GX->ub[1]&0x3f;
+            EX->q[0]>>tmp8u;
+            EX->q[0]&=(1<<(tmp8s+1)-1);
+        }
+        break;
 
     case 0x7C:  /* HADDPD Gx, Ex */
         nextop = F8;

diff --git a/src/emu/x64runf20f.c b/src/emu/x64runf20f.c
@@ -36,6 +36,7 @@ uintptr_t RunF20F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step)
     uint8_t tmp8u;
     int32_t tmp32s;
     int64_t tmp64s0, tmp64s1;
+    uint64_t tmp64u;
     reg64_t *oped, *opgd;
     sse_regs_t *opex, *opgx, eax1;
     mmx87_regs_t *opgm;
@@ -88,7 +89,12 @@ uintptr_t RunF20F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step)
             GX->d[0] = ED->sdword[0];
         }
         break;
-
+    case 0x2B:  /* MOVNTSD Ex, Gx */
+        nextop = F8;
+        GETEX8(0);
+        GETGX;
+        EX->q[0] = GX->q[0];
+        break;
     case 0x2C:  /* CVTTSD2SI Gd, Ex */
         nextop = F8;
         _GETEX(0);
@@ -306,6 +312,41 @@ uintptr_t RunF20F(x64emu_t *emu, rex_t rex, uintptr_t addr, int *step)
         }
         break;
 
+    case 0x78:  /* INSERTQ Ex, Gx, ib, ib */
+        // AMD only
+        nextop = F8;
+        if(!box64_cputype || !(MODREG)) {
+            #ifndef TEST_INTERPRETER
+            emit_signal(emu, SIGILL, (void*)R_RIP, 0);
+            #endif
+        } else {
+            GETGX;
+            GETEX(2);
+            tmp8u = F8&0x3f;
+            tmp8s = F8&0x3f;
+            tmp64u = (1<<(tmp8s+1)-1);
+            EX->q[0] &=~(tmp64u<<tmp8u);
+            EX->q[0] |= (GX->q[0]&tmp64u)<<tmp8u;
+        }
+        break;
+    case 0x79:  /* INSERTQ Ex, Gx */
+        // AMD only
+        nextop = F8;
+        if(!box64_cputype || !(MODREG)) {
+            #ifndef TEST_INTERPRETER
+            emit_signal(emu, SIGILL, (void*)R_RIP, 0);
+            #endif
+        } else {
+            GETGX;
+            GETEX(2);
+            tmp8u = GX->ub[8]&0x3f;
+            tmp8s = GX->ub[9]&0x3f;
+            tmp64u = (1<<(tmp8s+1)-1);
+            EX->q[0] &=~(tmp64u<<tmp8u);
+            EX->q[0] |= (GX->q[0]&tmp64u)<<tmp8u;
+        }
+        break;
+
     case 0x7C:  /* HADDPS Gx, Ex */
         nextop = F8;
         _GETEX(0);

diff --git a/src/emu/x64runf30f.c b/src/emu/x64runf30f.c
@@ -98,7 +98,12 @@ uintptr_t RunF30F(x64emu_t *emu, rex_t rex, uintptr_t addr)
         else
             GX->f[0] = ED->sdword[0];
         break;
-
+    case 0x2B:  /* MOVNTSS Ex Gx */
+        nextop = F8;
+        GETEX4(0);
+        GETGX;
+        EX->ud[0] = GX->ud[0];
+        break;
     case 0x2C:  /* CVTTSS2SI Gd, Ex */
         nextop = F8;
         GETEX(0);

diff --git a/src/tools/my_cpuid.c b/src/tools/my_cpuid.c
@@ -519,7 +519,7 @@ void my_cpuid(x64emu_t* emu, uint32_t tmp32u)
                         | 1<<1      // cmplegacy?
                         | 1<<2      // securevm
                         | 1<<5      // ABM (LZCNT)
-                        //| 1<<6      // SSE4a (extrq, instrq, movntss, movntsd)
+                        | 1<<6      // SSE4a (extrq, instrq, movntss, movntsd)
                         //| 1<<7      // misaligned SSE
                         | 1<<8      // 3DNowPrefetch
                         //| 1<<10     // IBS