Merge pull request #24 from jbrandwood/master

Latest updates from my fork.

examples/asm/elmer/Makefile

@@ -2,9 +2,11 @@
 #
 
 PREREQS = ipl-scd
-SUBDIRS = rom-bare-tiatest rom-bare-vdctest scd-bios-hello scd-bios-hello-error \
+SUBDIRS = rom-bare-buftest rom-bare-mwrtest rom-bare-rcrtest rom-bare-tiatest \
           rom-core-hello rom-core-okitest \
-          cd-core-1stage cd-core-2stage scd-core-1stage scd-core-1stage-error \
+          scd-bios-hello scd-bios-hello-error \
+          cd-core-1stage cd-core-2stage cd-core-scsitest \
+          scd-core-1stage scd-core-1stage-error \
           scd-core-2stage scd-core-2stage-error scd-core-fastcd \
           rom-kickc-hello rom-kickc-shmup ted2-core-hwdetect ted2-core-sdcard \
           ted2-core-gulliver

examples/asm/elmer/README.md

@@ -14,12 +14,18 @@ This directory contains a number of example programs and utilities for developin
 * ted2-bios-usbcd
   - A modified System Card 3.0 HuCARD that runs a CD-ROM overlay uploaded through USB, rather than loading it from CD-ROM.
 
+* rom-bare-buftest
+  - A HuCARD ROM to compare a PC Engine emulator's buffered VDC reading with real PC Engine console hardware.
+
+* rom-bare-mwrtest
+  - A HuCARD ROM to compare a PC Engine emulator's VDC VRAM read/write timings with real PC Engine console hardware.
+
+* rom-bare-rcrtest
+  - A HuCARD ROM to compare a PC Engine emulator's RCR interrupt handling with real PC Engine console hardware.
+
 * rom-bare-tiatest
   - A HuCARD ROM to compare a PC Engine emulator's TIA-to-VDC cycle timing with real PC Engine console hardware.
 
-* rom-bare-vdctest
-  - A HuCARD ROM to compare a PC Engine emulator's VDC RCR interrupt handling with real PC Engine console hardware.
-
 * rom-core-okitest
   - A HuCARD ROM to compare a PC Engine emulator's ADPCM playback flags and ADPCM write speed with real PC Engine console hardware.
 
@@ -47,6 +53,9 @@ The "CORE(not TM)" PC Engine library is a small and configurable set of library
 * cd-core-2stage
   - A simple example of creating an ISO for a CD-ROM, and loading the "CORE(not TM)" kernel code in a startup overlay.
 
+* cd-core-scsitest
+  - A CD-ROM and a HuCARD for testing some low-level details of the PC Engine's SCSI CD-ROM behavior.
+
 * scd-core-1stage
   - A simple example of creating an ISO for a Super CD-ROM, and loading the "CORE(not TM)" kernel code from the overlay program.
 

examples/asm/elmer/cd-core-2stage/Makefile

@@ -7,7 +7,7 @@ AFLAGS ?= -newproc -strip -m -l 2 -S -overlay
 SRC1_INC = pceas.inc pcengine.inc core.inc core-startup.asm core-kernel.asm joypad.asm
 SRC1_OVL = core-stage1.asm core-config.inc
 
-SRC2_INC = pceas.inc pcengine.inc core.inc core-startup.asm core-kernel.asm joypad.asm
+SRC2_INC = pceas.inc pcengine.inc core.inc core-startup.asm core-kernel.asm joypad.asm unpack-zx0.asm
 SRC2_OVL = stage2.asm core-config.inc
 
 SRC_ISO  = core-stage1.bin stage2.ovl

examples/asm/elmer/cd-core-2stage/stage2.asm

@@ -65,6 +65,12 @@ CHR_0x20	=	CHR_ZERO + 32		; ASCII ' ' CHR tile #.
 
 USING_STAGE1	=	1
 
+		;
+		; Since we don't use it here, let's verify that this works.
+		;
+
+SUPPORT_ZX0VRAM	=	0			; Include decompress-to-VRAM?
+
 		;
 		; Include the library, reading the project's configuration
 		; settings from the local "core-config.inc", if it exists.

examples/asm/elmer/cd-core-scsitest/Makefile

@@ -0,0 +1,19 @@
+all: core-scsitest.iso scsitest.pce
+
+include ../Make_ex.inc
+
+AFLAGS ?= -newproc -strip -m -l 2 -S
+
+SRC_INC = pceas.inc pcengine.inc core.inc core-startup.asm core-kernel.asm joypad.asm adpcm.asm cdrom.asm
+SRC_OVL = scsitest.asm core-config.inc
+
+SRC_ISO = scsitest.ovl ../data/alice.vdc ../data/alice.ram ../data/umbrella-16k.vox
+
+core-scsitest.iso: $(SRC_ISO)
+	$(IL) core-scsitest.iso -ipl="test-CD CD-ROM2",0x4000,0x4000,0,1,2,3,4 -asm $(SRC_ISO)
+
+scsitest.ovl: $(SRC_OVL) $(SRC_INC) scsitest.pce
+	$(AS) $(AFLAGS) -cd -overlay scsitest.asm
+
+scsitest.pce: $(SRC_OVL) $(SRC_INC)
+	$(AS) $(AFLAGS) -raw scsitest.asm

examples/asm/elmer/cd-core-scsitest/core-scsitest.cue

@@ -0,0 +1,3 @@
+FILE core-scsitest.iso BINARY
+  TRACK 01 MODE1/2048
+    INDEX 01 00:00:00