Cl2-chisel(Developing)

Cl2-chisel is a low-power MCU(Micro Control Unit)-level processor based on Chisel6, built by mill.

Currently supporting RV32I/M/C.

Sub-directories Overview

cl2-chisel
|-cl2/src						        // Source Code
|--cc							          // For Verilator Simulation
|--scala						        // Chisel Code
|-test
|--riscv-arch-test-am				// RISC-V instruction test
|-scripts						
|-utils							
|-vsrc							        // Store Verilog Generated by mill
|-Makefile

Default make

Run default make to compile chisel and generate binary.

Run make verilog to generate verilog code. The output file is ./vsrc.

Run make gen to simulate verilog and generate binary.

Simulation

We use Verilator for simulation, with the related stimulus tests stored in ./src/cc.

Run make sim to launch simulation by verilator_sim.mk in ./scripts. The default image is dummy.

You can either use our ready-to-run image for simulation or build image yourself in AM project.

Test

Before test, run git submodule update to get RISC-V Instruction Test. You should modify Makefile in ./test/riscv-arch-test-am as follow:

--  TEST_DIR = $(TEST_ISA:%=./riscv-test-suite/rv$(XLEN)$(BASE_ISA)_m/%/src)
++  TEST_DIR = $(TEST_ISA:%=.test/riscv-arch-test-am/riscv-test-suite/rv$(XLEN)$(BASE_ISA)_m/%/src)

--  include ${AM_HOME}/Makefile" > $@
++  include ../Makefille" /Makefile" > $@

You can alse select different extensions in RISC-V by modifying TEST_ISA in this Makefile, the default is I M C.