Required SRAM size for CVA6

[AAnand-Git]

Hi,

I am trying to trace the size of SRAM required for L1-Cache for CVA6 design.

Here the SRAM configuration I observed after tracing through CVA6 Design.
CVA6 SRAM unit size is parameterized with default value and can be controlled from configuration file.

With current configuration, I found

Each SRAM Unit = 16384 Bit = 16KB
NumWord x DataWidth (bit) = 256 x 64

Instruction cache

Size = Associativity x (Data + Tag) = 4 x (32768 + 16348) =196464 Bit
Associativity = 4
Data = 2 x Each SRAM Unit = 2 x 256 x 64 = 32768
Tag = 1 x Each SRAM Unit = 1 x 256 x 64 = 16348
Data cache

Size = (Associativity x (Data + Tag)) + Dirty (8 x (32768 + 16348)) + 16348 = 409278 Bit
Associativity = 8
Data = 2 x Each SRAM Unit = 2 x 256 x 64 = 32768
Tag = 1 x Each SRAM Unit = 1 x 256 x 64 = 16348
Dirty = 1 x Each SRAM Unit = 1 x 256 x 64 = 16348
Total L1 Cache size = Instruction cache Size + Data cache Size = 196464 Bit + 409278 Bit = 605742 Bit = 591.5449291 KB

Can you suggest if a SRAM instance is of 16KB (256 x 64 bits) be used to create L1 instruction and data cache.