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OpenHW Group

README.md

About OpenHW Group

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices. Please see our website for membership information, latest news, and further resources.

OpenHW Group CORE-V Family of Open-Source RISC-V Cores

Below is the CORE-V Roadmap of Application class and Embedded class cores. Please see core-v-cores repo for roadmap details.

Project Repositories Table of Contents

Working Group Repo Description
Cores TG Core-v-cores roadmap
CTG meetings and minutes
In Active Development CVA6 6-stage, application-class and embedded-class configurable core family
CVW 5-stage, application-class core with education focus
CV32E40PV2 4-stage, embedded-class core extending CV32E40Pv1 with FPU and PULP extensions
CV32E40S 4-stage, embedded-class core with security focus
CV32E20 2-stage, embedded-class microcontroller core and core complex
CV32E40PX (repo TBD) 4-stage, embedded-class core extending CV32E40Pv2 with RVB/RVK/RVP and CV-X-IF
Completed CV32E40P 4-stage, embedded-class core implementing PULP extensions at TRL5
CVA5 5-stage, FPGA-optimized application-class core at TRL3
CV32E41P 4-stage, embedded-class core prototyping Zfinx and Zce at TRL3
Inactive project CV32E40X 4-stage, embedded-class core supporting X-Interface
Verification TG VTG meetings and minutes
CORE-V Verif Common test bench for OpenHW Cores
FORCE RISC-V Advanced RISC-V instruction set generator
Software TG SWTG meetings and minutes
CORE-V GNU Tools GNU Tools Project for embedded-class CORE-V cores
CORE-V LLVM LLVM Tools Project for embedded-class CORE-V cores
CORE-V FreeRTOS Kernel FreeRTOS Kernel for embedded-class CORE-V cores
CORE-V FreeRTOS FreeRTOS for embedded-class CORE-V cores
CORE-V QEMU QEMU emulator for CORE-V-MCU
CORE-V SDK SDK and IDE for 4-stage CORE-V cores
CVA6 SDK Software tools for the CVA6 core
Interconnect TG
CV-HPDCACHE High performance L1 Data Cache
CV-MESH (repo TBD) Coherency framework based on Open Piton
CV-TCCC Tightly-coupled cache coherence for CVA6
CORE-V VISION APU (repo TBD) Machine learning SoC including CVA6 and CV-VEC
CVA6-Platform Multi-core CVA6 with CV-MESH intended for software testing
CORE-V-POLARA-APU Multicore CVA6/CVVEC ASIC with CV-MESH
CORE-V-POLARA-DEVKIT (repo TBD) Development board for Polara APU
Hardware TG HWTG meetings and minutes
CORE-V-MCU ASIC and FPGA MCU implementation of CV32E40P
CORE-V-MCU-DEVKIT Devkit for CORE-V-MCU
Technical Working Group OpenHW project dashboard
Project Description Folders
OpenHW Project process and templates

Popular repositories Loading

  1. cva6 cva6 Public

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    Assembly 2.3k 689

  2. cv32e40p cv32e40p Public

    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

    SystemVerilog 963 420

  3. core-v-verif core-v-verif Public

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 446 222

  4. cvfpu cvfpu Public

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

    SystemVerilog 437 115

  5. cvw cvw Public

    CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

    SystemVerilog 269 195

  6. force-riscv force-riscv Public

    Instruction Set Generator initially contributed by Futurewei

    C++ 265 57

Repositories

Showing 10 of 61 repositories
  • cvw Public

    CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

    openhwgroup/cvw’s past year of commit activity
    SystemVerilog 269 195 12 3 Updated Nov 14, 2024
  • cvw-arch-verif Public

    The purpose of the repo is to support CORE-V Wally architectural verification

    openhwgroup/cvw-arch-verif’s past year of commit activity
    SystemVerilog 3 20 6 4 Updated Nov 14, 2024
  • core-v-verif Public

    Functional verification project for the CORE-V family of RISC-V cores.

    openhwgroup/core-v-verif’s past year of commit activity
    Assembly 446 222 123 (7 issues need help) 14 Updated Nov 14, 2024
  • cva6 Public

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    openhwgroup/cva6’s past year of commit activity
    Assembly 2,281 689 190 (1 issue needs help) 10 Updated Nov 14, 2024
  • core-v-sw Public

    Main Repo for the OpenHW Group Software Task Group

    openhwgroup/core-v-sw’s past year of commit activity
    15 EPL-2.0 28 5 0 Updated Nov 11, 2024
  • cv32e40s-dv Public

    CV32E40S Design-Verification environment

    openhwgroup/cv32e40s-dv’s past year of commit activity
    Assembly 0 Apache-2.0 1 1 0 Updated Nov 11, 2024
  • cv32e40x Public

    4 stage, in-order, compute RISC-V core based on the CV32E40P

    openhwgroup/cv32e40x’s past year of commit activity
    SystemVerilog 213 51 30 (3 issues need help) 5 Updated Nov 6, 2024
  • programs Public

    Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    openhwgroup/programs’s past year of commit activity
    HTML 195 96 9 7 Updated Nov 4, 2024
  • cv-hpdcache Public

    RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

    openhwgroup/cv-hpdcache’s past year of commit activity
    SystemVerilog 59 18 4 1 Updated Nov 1, 2024
  • cv32e40s Public

    4 stage, in-order, secure RISC-V core based on the CV32E40P

    openhwgroup/cv32e40s’s past year of commit activity
    SystemVerilog 131 22 1 1 Updated Oct 31, 2024
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