add: csdk update e7d55248

openLuat · Dec 24, 2024 · 4215cda · 4215cda
1 parent db9f7bf
commit 4215cda
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Showing 124 changed files with 47,363 additions and 45,107 deletions.
diff --git a/PLAT/core/code/fota_code.c b/PLAT/core/code/fota_code.c
@@ -21,7 +21,7 @@
 #include "fota_chksum.h"
 #include "fota_custom.h"
 #include "fota_nvm.h"
-
+extern uint8_t FLASH_write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
 /*----------------------------------------------------------------------------*
  *                    MACROS                                                  *
  *----------------------------------------------------------------------------*/
@@ -470,11 +470,19 @@ static int32_t fotaNvmNfsWrite(uint32_t zid, uint32_t offset, uint8_t *buf, uint
 
     if(zid == FOTA_NVM_ZONE_CP)
     {
+#ifdef TYPE_EC718U
+    	retValue = FLASH_write(buf, currAddr, currLen);
+#else
         retValue = BSP_QSPI_WRITE_CP_FLASH(buf, currAddr, currLen);
+#endif
     }
     else
     {
+#ifdef TYPE_EC718U
+    	retValue = FLASH_write(buf, currAddr, currLen);
+#else
         retValue = BSP_QSPI_WRITE_AP_FLASH(buf, currAddr, currLen);
+#endif
     }
 
     return (retValue == QSPI_OK ? FOTA_EOK : FOTA_EFLWRITE);
@@ -630,6 +638,10 @@ static int32_t fotaNvmPrepareDfu(FotaDefPrepareDfu_t *preDfu)
                 return FOTA_EOK;
             }
         }
+        else
+        {
+            ECPLAT_PRINTF(UNILOG_FOTA, FOTA_NVM_PREP_DFU_4, P_WARNING, "prep DFU: save err!\n");
+        }
     }
 
     retCode = FOTA_EPERM;
@@ -1265,7 +1277,11 @@ int32_t fotaNvmDoExtension(uint32_t flags, void *args)
 #ifdef __BL_MODE__
 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
 {
-    return FLASH_write(pData, WriteAddr, Size);
+#ifdef TYPE_EC718U
+	return FLASH_write(pData, WriteAddr, Size);
+#else
+    return FLASH_writeBl(pData, WriteAddr, Size);
+#endif
 }
 
 uint8_t  BSP_QSPI_Erase_Sector(uint32_t SectorAddress)
@@ -1276,6 +1292,14 @@ uint8_t  BSP_QSPI_Erase_Sector(uint32_t SectorAddress)
 
 uint32_t BL_OTAInfoAddress(void) {return (BOOTLOADER_FLASH_LOAD_ADDR + BOOTLOADER_FLASH_LOAD_SIZE);}
 uint32_t BL_DFotaAddress(void) {return (FLASH_FOTA_REGION_START);}
+uint8_t BL_WriteFlash(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
+{
+#ifdef TYPE_EC718U
+	return FLASH_write(pData, WriteAddr, Size);
+#else
+    return FLASH_writeBl(pData, WriteAddr, Size);
+#endif
+}
 #ifdef TYPE_EC718M
 uint32_t BL_MemAddress(void) {return (PSRAM_P2_START_ADDR);}
 #else

diff --git a/PLAT/core/ld/ec7xxxm_0h00_flash.c b/PLAT/core/ld/ec7xxxm_0h00_flash.c
@@ -101,7 +101,7 @@ SECTIONS
         Load$$LOAD_AP_PSRAM_P2_DATA$$Base = LOADADDR(.load_ap_psram_p2_data);
         Image$$LOAD_AP_PSRAM_P2_DATA$$Base = .;
         *(.cust_sect_ap_psram_p2_data.*)
-        *(EXCLUDE_FILE(*libc*.a) .data*)
+        *(EXCLUDE_FILE(*libc_nano.a *libc.a) .data*)
         . = ALIGN(4);
     } >PSRAM_P2_AREA AT>FLASH_AREA
     Image$$LOAD_AP_PSRAM_P2_DATA$$Length = SIZEOF(.load_ap_psram_p2_data);
@@ -111,7 +111,7 @@ SECTIONS
         . = ALIGN(4);
         Image$$LOAD_AP_PSRAM_P2_ZI$$Base = .;
         *(.cust_sect_ap_psram_p2_bss.*)
-        *(EXCLUDE_FILE(*libc*.a) .bss*)
+        *(EXCLUDE_FILE(*libc_nano.a *libc.a) .bss*)
         . = ALIGN(4);
         Image$$LOAD_AP_PSRAM_P2_ZI$$Limit = .;
     } >PSRAM_P2_AREA
@@ -383,6 +383,7 @@ SECTIONS
         *(.sect_slpman_data.*)
         *(.sect_bsp_usart_data.*)
         *(.sect_bsp_lpusart_data.*)
+        *(.sect_bsp_can_data.*)
         *(.sect_timer_data.*)
         *(.sect_dma_data.*)
         *(.sect_adc_data.*)
@@ -420,6 +421,7 @@ SECTIONS
         *(.sect_slpman_bss.*)
         *(.sect_bsp_usart_bss.*)
         *(.sect_bsp_lpusart_bss.*)
+        *(.sect_bsp_can_bss.*)
         *(.sect_timer_bss.*)
         *(.sect_dma_bss.*)
         *(.sect_adc_bss.*)
@@ -490,29 +492,27 @@ SECTIONS
         Image$$LOAD_AP_FPSRAM_P1_ZI$$Limit = .;
     } >PSRAM_P1_AREA
 
-    . = ALIGN(4);
-    PROVIDE(end_ap_data = .|PSRAM_PCACHE1_BASE);
-    PROVIDE(start_up_buffer = up_buf_start);
-    .unload_voiceEng_buffer start_up_buffer (NOLOAD):
+	.unload_voiceEng_buffer (.|PSRAM_PCACHE1_BASE) (NOLOAD):
     {
         . = ALIGN(4);
         *(.sect_voiceEngSharebuf.*)
         . = ALIGN(4);
     } >PSRAM_P1_AREA
 
-    .unload_up_buffer (up_buf_start+SIZEOF(.unload_voiceEng_buffer)) (NOLOAD):
+    .unload_up_buffer (.|PSRAM_PCACHE1_BASE) (NOLOAD):
     {
         . = ALIGN(4);
         *(.sect_catShareBuf_data.*)
         *(.sect_ccio_buf.*)
         . = ALIGN(4);
     } >PSRAM_P1_AREA
 
-    PROVIDE(end_up_buffer = . );
+    . = ALIGN(4);
+    PROVIDE(end_ap_data = .|PSRAM_PCACHE1_BASE);
+    PROVIDE(start_up_buffer = up_buf_start);
     heap_size = start_up_buffer - end_ap_data;
     asmbFlexSize = CP_AONMEMBACKUP_START_ADDR - asmb_flex_area;
     //ASSERT(heap_size>=min_heap_size_threshold,"ap use too much ram, heap less than min_heap_size_threshold!")
-    ASSERT(end_up_buffer<=PSRAM_APMEM_END_ADDR,"ap use too much ram, exceed to PSRAM_APMEM_END_ADDR")
     #if !defined FEATURE_IMS_ENABLE
     ASSERT(asmbFlexSize>=0x1000, "we should reserve at least 4KB for user")
     #endif

diff --git a/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armcc.h b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_armcc.h
@@ -97,6 +97,7 @@
 #ifndef   __RESTRICT
   #define __RESTRICT                             __restrict
 #endif
+#define ASM_CALLER                               
 
 /* ###########################  Core Function Access  ########################### */
 /** \ingroup  CMSIS_Core_FunctionInterface

diff --git a/PLAT/device/target/board/common/ARMCM3/inc/cmsis_gcc.h b/PLAT/device/target/board/common/ARMCM3/inc/cmsis_gcc.h
@@ -64,6 +64,8 @@
 #ifndef   __PACKED_UNION
   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
 #endif
+#define ASM_CALLER                               __attribute__((noinline, optimize("-fno-ipa-ra")))
+
 #ifndef   __UNALIGNED_UINT32        /* deprecated */
   #pragma GCC diagnostic push
   #pragma GCC diagnostic ignored "-Wpacked"

diff --git a/PLAT/device/target/board/ec7xx_0h00/ap/gcc/version.h b/PLAT/device/target/board/ec7xx_0h00/ap/gcc/version.h
@@ -1,7 +1,7 @@
 #define SDK_MAJOR_VERSION   "001" // For Major version	   
 #define SDK_MINOR_VERSION   "017" // For minor version	   
 #define SDK_RA_VERSION      "xxx" // For jenkins release use	   
-#define SDK_PATCH_VERSION   "p001.009"   // For patch verion, modify when patch release
+#define SDK_PATCH_VERSION   "p001.010"   // For patch verion, modify when patch release
 #define EVB_MAJOR_VERSION   "1"	   
 #define EVB_MINOR_VERSION   "0"	   
 #if defined CHIP_EC718	   

diff --git a/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_716s.h b/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_716s.h
@@ -404,7 +404,7 @@ flash xip address(from ap/cp view): 0x00800000---0x00a00000
 #define MSMB_CPMEM_START_ADDR           (0x004CA000)
 #endif
 #define MSMB_CPMEM_LENGTH               (MSMB_END_ADDR-MSMB_CPMEM_START_ADDR)
-#define MSMB_CPDATA_START_ADDR          (0x004ED000)
+#define MSMB_CPDATA_START_ADDR          (0x004ED800)
 #define XP_SHAREINFO_BASE_ADDR          (0x004FE000)
 #define XP_DBGRESERVED_BASE_ADDR        (0x004FEF00)
 #define IPC_SHAREDMEM_START_ADDR        (0x004FF000)

diff --git a/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_718hm.h b/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_718hm.h
@@ -368,7 +368,7 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #define PSRAM_AREA_P2_OFFSET            (0x00140000)
 #endif // OPEN_CPU_MODE
 
-#define PSRAM_AREA_END_OFFSET           (0x00400000)
+#define PSRAM_AREA_END_OFFSET           (0x00800000)
 
 #define PSRAM_P0_START_ADDR            (PSRAM_START_ADDR|PSRAM_AREA_P1_OFFSET)
 #define PSRAM_P1_START_ADDR            (PSRAM_START_ADDR|PSRAM_AREA_P1_OFFSET)
@@ -400,12 +400,12 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #define min_heap_size_threshold 0x5F000//ims heap(280KB) will also use heap
 #endif
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0xa0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
 #if defined(FEATURE_IMS_CC_ENABLE) || defined(FEATURE_AUDIO_ENABLE)
-#define up_buf_start 0xa0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0xa0c6000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 
 #endif
@@ -414,20 +414,20 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #define min_heap_size_threshold 0x19000
 #if defined (FEATURE_AMR_CP_ENABLE) && defined (FEATURE_VEM_CP_ENABLE)
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0x0a093000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0x0a094000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #else
-#define up_buf_start 0x0a07d000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #endif
 
 #define UP_BUF_MAX_SIZE 0x3CA00//only upbuf size, need another 512B for other buf also in this region
 
 #else
 #define min_heap_size_threshold 0x20000
-#define up_buf_start 0x0a080000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #define UP_BUF_MAX_SIZE 0x66D00//only upbuf size, need another 512B for other buf also in this region
 #endif
 

diff --git a/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_718pm.h b/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_718pm.h
@@ -386,7 +386,7 @@ flash xip address(from both ap/cp view): 0x00800000---0x00c00000
 #define SHARED_MEM_START_ADDR          (PSRAM_START_ADDR|PSRAM_AREA_P0_OFFSET)
 #define SHARED_MEM_LENGTH              (PSRAM_AREA_APCP_SHARED_MEM-PSRAM_AREA_P0_OFFSET)
 
-#define PSRAM_APMEM_END_ADDR           (PSRAM_START_ADDR|PSRAM_PCACHE1_BASE|PSRAM_AREA_P2_OFFSET)//(0x0a140000)
+#define PSRAM_APMEM_END_ADDR           (PSRAM_START_ADDR|PSRAM_PCACHE1_BASE|PSRAM_AREA_P2_OFFSET)
 
 #define XP_SHAREINFO_BASE_ADDR          (0x08000000)
 #define XP_DBGRESERVED_BASE_ADDR        (0x08000f00)
@@ -401,13 +401,13 @@ flash xip address(from both ap/cp view): 0x00800000---0x00c00000
 #define min_heap_size_threshold 0x5F000//ims heap(280KB) will also use heap
 #endif
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0x0a0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
 
 #if defined(FEATURE_IMS_CC_ENABLE) || defined(FEATURE_AUDIO_ENABLE)
-#define up_buf_start 0xa0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0xa0c6000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 
 #endif
@@ -416,20 +416,20 @@ flash xip address(from both ap/cp view): 0x00800000---0x00c00000
 #define min_heap_size_threshold 0x19000
 #if defined (FEATURE_AMR_CP_ENABLE) && defined (FEATURE_VEM_CP_ENABLE)
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0x0a093000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0x0a094000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #else
-#define up_buf_start 0x0a07d000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #endif
 
 #define UP_BUF_MAX_SIZE 0x3CA00//only upbuf size, need another 512B for other buf also in this region
 
 #else
 #define min_heap_size_threshold 0x20000
-#define up_buf_start 0x0a080000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #define UP_BUF_MAX_SIZE 0x66D00//only upbuf size, need another 512B for other buf also in this region
 
 #endif

diff --git a/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_718um.h b/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_718um.h
@@ -400,12 +400,12 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #define min_heap_size_threshold 0x5F000//ims heap(280KB) will also use heap
 #endif
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0xa0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
 #if defined(FEATURE_IMS_CC_ENABLE) || defined(FEATURE_AUDIO_ENABLE)
-#define up_buf_start 0xa0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0xa0c6000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 
 #endif
@@ -414,20 +414,20 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #define min_heap_size_threshold 0x19000
 #if defined (FEATURE_AMR_CP_ENABLE) && defined (FEATURE_VEM_CP_ENABLE)
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0x0a093000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0x0a094000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #else
-#define up_buf_start 0x0a07d000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #endif
 
 #define UP_BUF_MAX_SIZE 0x3CA00//only upbuf size, need another 512B for other buf also in this region
 
 #else
 #define min_heap_size_threshold 0x20000
-#define up_buf_start 0x0a080000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #define UP_BUF_MAX_SIZE 0x66D00//only upbuf size, need another 512B for other buf also in this region
 #endif
 

diff --git a/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_csdk_716s.h b/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_csdk_716s.h
@@ -270,7 +270,7 @@ flash xip address(from ap/cp view): 0x00800000---0x00a00000
 #define MSMB_CPMEM_START_ADDR           (0x004CA000)
 
 #define MSMB_CPMEM_LENGTH               (MSMB_END_ADDR-MSMB_CPMEM_START_ADDR)
-#define MSMB_CPDATA_START_ADDR          (0x004ED000)
+#define MSMB_CPDATA_START_ADDR          (0x004ED800)
 #define XP_SHAREINFO_BASE_ADDR          (0x004FE000)
 #define XP_DBGRESERVED_BASE_ADDR        (0x004FEF00)
 #define IPC_SHAREDMEM_START_ADDR        (0x004FF000)

diff --git a/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_csdk_718hm.h b/PLAT/device/target/board/ec7xx_0h00/common/inc/mem_map_csdk_718hm.h
@@ -328,11 +328,11 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #if defined (FEATURE_AMR_CP_ENABLE) && defined (FEATURE_VEM_CP_ENABLE)
 #define PSRAM_AREA_P0_CP_OFFSET         (0x4e400)
 #define PSRAM_AREA_P1_OFFSET            (0x4e400)
-#define PSRAM_AREA_P2_OFFSET            (0x00140000)
+#define PSRAM_AREA_P2_OFFSET            (0x00d0000)
 #else
 #define PSRAM_AREA_P0_CP_OFFSET         (0x34400)
 #define PSRAM_AREA_P1_OFFSET            (0x34400)
-#define PSRAM_AREA_P2_OFFSET            (0x00e0000)
+#define PSRAM_AREA_P2_OFFSET            (0x00b0000)
 #endif
 
 
@@ -368,12 +368,12 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #define min_heap_size_threshold 0x5F000//ims heap(280KB) will also use heap
 #endif
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0xa0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
 #if defined(FEATURE_IMS_CC_ENABLE) || defined(FEATURE_AUDIO_ENABLE)
-#define up_buf_start 0xa0e0000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0xa0c6000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 
 #endif
@@ -382,20 +382,20 @@ flash xip address(from both ap/cp view): 0x00800000---0x01000000
 #define min_heap_size_threshold 0x19000
 #if defined (FEATURE_AMR_CP_ENABLE) && defined (FEATURE_VEM_CP_ENABLE)
 #if FEATURE_SUPPORT_APP_PCM_MEM_POOL//hal app mem pool 640*3+8align to 2K
-#define up_buf_start 0x0a093000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #else
-#define up_buf_start 0x0a094000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #else
-#define up_buf_start 0x0a07d000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #endif
 #endif
 
 #define UP_BUF_MAX_SIZE 0x3CA00//only upbuf size, need another 512B for other buf also in this region
 
 #else
 #define min_heap_size_threshold 0x20000
-#define up_buf_start 0x0a080000  // should be 4 byte align
+#define up_buf_start PSRAM_APMEM_END_ADDR  // should be 4 byte align
 #define UP_BUF_MAX_SIZE 0x66D00//only upbuf size, need another 512B for other buf also in this region
 #endif