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SERV 1.1.0
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@olofk olofk released this 09 Aug 21:49
· 146 commits to main since this release
1.1.0
8e07354

New features

Many of the new features of SERV 1.1.0 are described in the latest SERV video SERV : RISC-V for a fistful of gates but below here you will find a complete list of major changes from SERV 1.0

Serving

A new helper component called the Serving SoClet has been created to make it easy to integrate SERV into FPGA designs. Serving consisting of SERV+register file+data/instruction memory and exposes a wishbone bus for connecting peripherals.

Servant

The SERV reference SoC, Servant, has gained support for the following new FPGA boards:

  • Xilinx zcu106
  • Radiona ULX3S 85k
  • Icezum Alhambra II
  • Gnarly Grey Upduino2
  • Saanlima pipistrello
  • Avnet LX9 Microboard
  • GsD OrangeCrab
  • Lattice iCEstick
  • Terasic DE0 Nano
  • Xilinx ac701
  • Muselab iCEsugar
  • Digilent CMOD-A7-35t
  • Arrow SoCkit
  • Arrow DECA Max10
  • Terasic DE10 Nano
  • Nandland Go

With this, the total number of officially supported boards is 21

Zephyr

Supports Zephyr 2.4. With this, instructions have been vastly simplified and all SERV-specific support code is contained separately within the SERV repository.

Other

  • Compatible with Xilinx ISE
  • Compatible with RISC-V compliance tests v1.0
  • New RESET_STRATEGY parameter to control the amount of reset to apply to the core
  • Github actions for CI

Optimizations

  • Approximately 20% smaller than SERV 1.0

Documentation

Almost all internal modules have been documented with a functional description and gate-accurate block diagrams. Important internal and external sequences have also been documented with timing diagrams. Source code is also heavily commented.

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