cleanup and unsigned_mod_l

offamitkumar · Oct 14, 2024 · 6f820ec · 6f820ec
1 parent 10243c5
commit 6f820ec
Showing 1 changed file with 23 additions and 6 deletions.
diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad
@@ -1309,7 +1309,6 @@ class CallStubImpl {
 %} // end source_hpp section
 
 source %{
-  long fubar = 0;
 
 #if !defined(PRODUCT)
 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
@@ -6267,9 +6266,6 @@ instruct udivI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp
     assert_different_registers(t, b, Z_R1_scratch);
 
     __ block_comment("unsigned_div {");
-    //__ stop("fucked up in unsigned integer division !!");
-    __ load_const_optimized(Z_R1_scratch, (uintptr_t)&fubar);
-    __ z_agsi(0, Z_R1_scratch, 1);
     __ z_lghi(t->predecessor(), 0); // set left most 32 bit to 0, see instruction description
     __ lgr_if_needed(t, a);
     __ z_dlr(t->predecessor()/* t is odd part of a register pair. */, b);
@@ -6345,7 +6341,6 @@ instruct udivL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
     Register b = $src$$Register;
     Register t = $dst$$Register;
     __ block_comment("unsigned_div_long {");
-    __ stop("fucked up in unsigned long division!!");
     __ z_dlgr(t->predecessor()/* t is odd part of a register pair. */, b);
     __ block_comment("} unsigned_div_long");
   %}
@@ -6423,7 +6418,7 @@ instruct umodI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp
   effect(KILL tmp, KILL cr);
   ins_cost(DEFAULT_COST);
   // TODO: s390 port size(VARIABLE_SIZE);
-  format %{ "UMOD_checked   $dst,$src1,$src2" %}
+  format %{ "UMOD   $dst,$src1,$src2" %}
   ins_encode %{
     Register a = $src1$$Register;
     Register b = $src2$$Register;
@@ -6432,6 +6427,7 @@ instruct umodI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp
 
     __ block_comment("unsigned_mod_integer {");
     __ z_lgfr(t->successor(), a);
+    __ z_lghi(t, 0);
     __ z_dlr(t/* t is even part of a register pair. */, b);
     __ block_comment("} unsigned_mod_integer");
   %}
@@ -6501,6 +6497,27 @@ instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
   ins_pipe(pipe_class_dummy);
 %}
 
+// Register Long Remainder
+instruct umodL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
+  match(Set dst (UModL src1 src2));
+  effect(KILL src1, KILL cr); // R0 is killed, too.
+  ins_cost(DEFAULT_COST);
+  // TODO: s390 port size(VARIABLE_SIZE);
+  format %{ "UMODG   $dst,$src1,$src2" %}
+  ins_encode %{
+    Register a = $src1$$Register;
+    Register b = $src2$$Register;
+    Register t = $dst$$Register;
+    assert(t->successor() == a, "(t,a) is an even-odd pair" );
+
+    __ block_comment("unsigned_mod_long {");
+    __ z_lghi(t, 0);
+    __ z_dlgr(t, b);
+    __ block_comment("} unsigned_mod_integer");
+  %}
+  ins_pipe(pipe_class_dummy);
+%}
+
 // Register Long Remainder
 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
   match(Set dst (ModL src1 src2));