unsigned integer division

offamitkumar · Oct 14, 2024 · 457a153 · 457a153
1 parent 8cb499d
commit 457a153
Showing 1 changed file with 22 additions and 0 deletions.
diff --git a/src/hotspot/cpu/s390/s390.ad b/src/hotspot/cpu/s390/s390.ad
@@ -6253,6 +6253,28 @@ instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, fl
   ins_pipe(pipe_class_dummy);
 %}
 
+// Unsigned Integer Register Division
+instruct udivI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
+  match(Set dst (UDivI src1 src2));
+  effect(KILL tmp, KILL cr);
+  // TODO: size(4);
+  format %{ "UDIV $dst, $src1,$src2" %}
+  ins_encode %{
+    Register a = $src1$$Register;
+    Register b = $src2$$Register;
+    Register t = $dst$$Register;
+    assert_different_registers(t, b);
+
+    __ block_comment("unsigned_div {");
+    __ stop("fucked up in unsigned integer division !!");
+    __ z_lghi(t-predecessor(), 0); // set left most 32 bit to 0, see instruction description
+    __ lgr_if_needed(t, a);
+    __ z_dlr(t->predecessor()/* t is odd part of a register pair. */, b);
+    __ block_comment("} unsigned_div");
+  %}
+  ins_pipe(pipe_class_dummy);
+%}
+
 // Long DIVMOD with Register, both quotient and mod results
 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
   match(DivModL dst1src1 src2);