Discern between devices with CPU CGB A and B revision SOCs

LICENSE

@@ -1,6 +1,7 @@
 MIT License
 
-Copyright (c) 2020 Matt Currie
+Copyright (c) 2020-2022 Matt Currie
+Copyright (c) 2022 Lior Halphon (LIJI32)
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

README.md

@@ -2,7 +2,7 @@
 
 Just a little Game Boy ROM which tries to determine which model/revision your device is.  
 
-It makes use of register values at boot, "extra OAM" differences, PPU quirks, and APU quirks that differ between device revisions.
+It makes use of register values at boot, "extra OAM" differences, PPU quirks, APU quirks, and OAM DMA bus conflicts that differ between device revisions.
 
 ## Limitations
 
@@ -16,7 +16,8 @@ Currently it cannot discern between all SoC revisions. Devices will be reported
 - SGB-CPU 01
 - CPU SGB2
 - CPU CGB
-- CPU CGB A/B
+- CPU CGB A
+- CPU CGB B
 - CPU CGB C
 - CPU CGB D
 - CPU CGB E
@@ -25,6 +26,10 @@ Currently it cannot discern between all SoC revisions. Devices will be reported
 
 ## Release Notes
 
+v0.4
+
+- Use an OAM DMA bus conflict to discern between devices with CPU CGB A and CPU CGB B revision SOCs. Thanks to [LIJI32](https://github.com/LIJI32/) for discovering this!
+
 v0.3
 
 - Use VRAM reads at the transition from PPU mode 3 to mode 0 discern between devices with CPU AGB 0/A/A E (AGB and GB Player) and CPU AGB B/B E (AGS) revisions
@@ -43,6 +48,7 @@ v0.2
 
 ## Credits
 
+- Thanks to Lior Halphon (LIJI32) for his research and [SameSuite](https://github.com/LIJI32/SameSuite) test ROMs.
 - Thanks to authors of [Gameboy sound hardware](https://gbdev.gg8.se/wiki/articles/Gameboy_sound_hardware) on the Gameboy Development Wiki.
 - Thanks to Joonas Javanainen (gekkio) for his [mooneye-gb](https://github.com/Gekkio/mooneye-gb/) test ROMs which document the register values at boot.
 - Written by Matt Currie. 

src/which.asm

@@ -58,7 +58,7 @@ SECTION "main", ROM0[$150]
 
 main::
     di
-    ld sp, $cfff
+    ld sp, $ffff
 
     ld [wInitialA], a
     ld a, b
@@ -70,7 +70,7 @@ main::
     call ResetCursor
     call LoadFont
 
-    print_string_literal "which.gb v0.3\n-------------\n\nseems to be a...\n\n"
+    print_string_literal "which.gb v0.4\n-------------\n\nseems to be a...\n\n"
 
     ld a, [wInitialA]
     cp $01
@@ -182,7 +182,16 @@ is_cgbABC::
     jr nz, is_cgbC
 
 is_cgbAB::
-    print_string_literal "CPU CGB A/B"
+    call check_cgb_a_or_b
+    cp $aa
+    jr nz, is_cgbB
+
+is_cgbA::
+    print_string_literal "CPU CGB A"
+    jp done
+
+is_cgbB::
+    print_string_literal "CPU CGB B"
     jp done
 
 is_cgbC::
@@ -322,4 +331,56 @@ check_agb_or_ags::
     ldh [rSCX], a
     pop af
 
-    ret
+    ret
+
+
+; Check some OAM DMA bus conflict behavior to test if it is a CGB CPU A or B.
+; Code lifted from LIJI32's `dma_write_timing-wram-C0ACA.asm` 
+;
+; @return a `$aa` on CPU CGB A, or `$00` on CPU CGB B
+check_cgb_a_or_b::
+    ld hl, ._HRAMRoutine
+    ld de, HRAMRoutine
+    ld bc, ._HRAMRoutineEnd - ._HRAMRoutine
+    call MemCopy
+
+    ld hl, ._VRAMRoutine
+    ld de, VRAMRoutine
+    ld bc, ._VRAMRoutineEnd - ._VRAMRoutine
+    call MemCopy
+
+    call .ResetWRAM
+    jp VRAMRoutine
+    
+._HRAMRoutine::
+    ld b, $40
+.wait:
+    dec b
+    jr nz, .wait
+    ret
+._HRAMRoutineEnd:
+
+._VRAMRoutine::
+    ld a, $c1
+    ld b, $aa
+    ld hl, $c155
+    ldh [rDMA], a
+    ld [hl], b
+    call HRAMRoutine
+    ld a, [$fe00]
+    ret
+._VRAMRoutineEnd:
+
+HRAMRoutine EQU $ff80
+VRAMRoutine EQU $a000 - (._VRAMRoutineEnd - ._VRAMRoutine)
+    
+.ResetWRAM::
+    ld a, $f0
+    ld [$fe00], a
+    ld hl, $c100
+    ld a, $10
+.loop:
+    ld [hl+], a
+    inc a
+    jr nz, .loop
+    ret