FPGA-accelerated Locality Sensitive Hashing

My Bachelor's Thesis @ ETH Zürich

Supervised by Prof. Dr. G. Alonso and Wenqi Jiang

The use of FPGA accelerators is a current topic in both academy and industry. Locality Sensitive Hashing (LSH) is a dimensionality reduction method commonly used in data analysis and has also many applications in machine learning. This work aims to test the possible accelerations of key components of an LSH algorithm, making use of the FPGA technology. With our implementations we were able to reach a speedup of 3.3x with respect to the CPU running time without loosing precision on the results.