Rk356x: Fix USB3 multiphy initialization for USB3 devices.

jaredmcneill · Apr 22, 2022 · 4bda76e · 4bda76e
1 parent c408d83
commit 4bda76e
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Showing 4 changed files with 14 additions and 2 deletions.
diff --git a/edk2-rockchip/Platform/Pine64/Quartz64/Quartz64.dsc b/edk2-rockchip/Platform/Pine64/Quartz64/Quartz64.dsc
@@ -442,6 +442,8 @@
   gRk356xTokenSpaceGuid.PcdEhc1Status|0xF
   gRk356xTokenSpaceGuid.PcdXhc0Status|0xF
   gRk356xTokenSpaceGuid.PcdXhc1Status|0xF
+  # Hack to work around broken USB3 port on Quartz64 model A
+  gRk356xTokenSpaceGuid.PcdMultiPhyUsb3DataBits|16
 
   #
   # Ethernet support

diff --git a/edk2-rockchip/Silicon/Rockchip/Rk356x/Library/MultiPhyLib/MultiPhyLib.c b/edk2-rockchip/Silicon/Rockchip/Rk356x/Library/MultiPhyLib/MultiPhyLib.c
@@ -17,6 +17,8 @@
 #include <Library/UefiBootServicesTableLib.h>
 #include <IndustryStandard/Rk356x.h>
 
+#define MULTIPHY_USB3_DATA_BITS     FixedPcdGet8 (PcdMultiPhyUsb3DataBits)
+
 #define MULTIPHY_REGISTER(RegNo)    (((RegNo) - 1) * 4)
 
 /* PIPE_PHY_GRF */
@@ -162,7 +164,12 @@ MultiPhySetModeUsb3 (
     /* Enable USB3 PHY mode, 16-bit data bus, 5Gbps */
     GrfUpdateRegister (PhyGrfBaseAddr + PIPE_PHY_GRF_PIPE_CON0,
                        PIPE_DATABUSWIDTH_MASK  | PIPE_PHYMODE_MASK | PIPE_RATE_MASK,
-                       PIPE_DATABUSWIDTH_16BIT | PIPE_PHYMODE_USB3 | PIPE_RATE_USB3_5GBPS);
+#if MULTIPHY_USB3_DATA_BITS == 16
+                       PIPE_DATABUSWIDTH_16BIT |
+#else
+                       PIPE_DATABUSWIDTH_32BIT |
+#endif
+                       PIPE_PHYMODE_USB3 | PIPE_RATE_USB3_5GBPS);
 
     /* Clock setup */
     Rate = CruGetPciePhyClockRate (Index);

diff --git a/edk2-rockchip/Silicon/Rockchip/Rk356x/Library/MultiPhyLib/MultiPhyLib.inf b/edk2-rockchip/Silicon/Rockchip/Rk356x/Library/MultiPhyLib/MultiPhyLib.inf
@@ -32,5 +32,6 @@
   CruLib
 
 [FixedPcd]
+  gRk356xTokenSpaceGuid.PcdMultiPhyUsb3DataBits
 
 [Guids]
diff --git a/edk2-rockchip/Silicon/Rockchip/Rk356x/Rk356x.dec b/edk2-rockchip/Silicon/Rockchip/Rk356x/Rk356x.dec
@@ -59,4 +59,6 @@
   gRk356xTokenSpaceGuid.PcdPcieNumLanes|0x1|UINT32|0x00000035
   # Pcds for RTC
   gRk356xTokenSpaceGuid.PcdRtcI2cBusBase|0|UINT32|0x00000040
-  gRk356xTokenSpaceGuid.PcdRtcI2cAddr|0|UINT8|0x00000041
+  gRk356xTokenSpaceGuid.PcdRtcI2cAddr|0|UINT8|0x00000041
+  # Pcds for MultiPhy
+  gRk356xTokenSpaceGuid.PcdMultiPhyUsb3DataBits|32|UINT8|0x00000050