Add CM_HAS_LSC_LOAD_L1RI_L3CA_HINT macro

Add CM_HAS_LSC_LOAD_L1RI_L3CA_HINT macro to check whether L1 read invalidate L3 cached combination is legal
intel · Mar 2, 2022 · 139a3a7 · 139a3a7
1 parent 25cbf42
commit 139a3a7
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/clang/lib/Headers/cm/include/cm/cm_has_instr.h b/clang/lib/Headers/cm/include/cm/cm_has_instr.h
@@ -182,6 +182,9 @@ namespace CheckVersion {
 #else
   #define CM_HAS_STOCHASTIC_ROUNDING_CONTROL CM_HAS_CONTROL(false)
 #endif
+#if (CM_GENX <= 1280)
+  #define CM_HAS_LSC_LOAD_L1RI_L3CA_HINT 1
+#endif
 
 #else  // CM_HAS_CONTROL
   CM_STATIC_ERROR(0, "Redeclaration of CM_HAS_CONTROL! It's used for control version of features!");