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Merge pull request #441 from mkroening/riscv
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feat: add 64-bit RISC-V support
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mkroening authored Nov 2, 2023
2 parents d6fa941 + c4fb0a8 commit ddc15ee
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3 changes: 3 additions & 0 deletions benches/micro/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,9 @@ default-features = false
[target.'cfg(target_arch = "aarch64")'.dependencies]
aarch64 = { version = "0.0.10", default-features = false }

[target.'cfg(target_arch = "riscv64")'.dependencies]
riscv = "0.10"

[target.'cfg(target_os = "linux")'.dependencies]
syscalls = { version = "0.6", default-features = false }

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6 changes: 6 additions & 0 deletions benches/micro/src/benches/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,12 @@ fn get_timestamp() -> u64 {
CNTPCT_EL0.get()
}

#[cfg(target_arch = "riscv64")]
#[inline]
fn get_timestamp() -> u64 {
riscv::register::time::read64()
}

extern "C" {
#[cfg(target_os = "hermit")]
fn sys_getpid() -> u32;
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