Merge pull request #228 from miek/amaranth_0.4

Pin Amaranth version 0.4 & clean-up dependencies

luna/gateware/interface/uart.py

@@ -9,7 +9,6 @@
 import unittest
 
 from amaranth   import Elaboratable, Module, Signal, Cat
-from amaranth_soc import wishbone, memory
 
 
 from ..stream       import StreamInterface
@@ -209,51 +208,6 @@ def test_burst_transmit(self):
         self.assertEqual((yield dut.idle), 1)
 
 
-class UARTTransmitterPeripheral(Elaboratable):
-    """ Wishbone-attached variant of our UARTTransmitter.
-
-    Attributes
-    ----------
-    tx: Signal(), output
-        The UART line to use for transmission.
-    bus: wishbone bus
-        Wishbone interface used for UART connections.
-
-    Parameters
-    ----------
-    divisor: int
-        number of `sync` clock cycles per bit period
-    """
-
-    # TODO: include a variant of misoc/LiteX's autoregister mechanism
-
-    def __init__(self, divisor):
-        self.divisor = divisor
-
-        #
-        # I/O port
-        #
-        self.tx  = Signal()
-        self.bus = wishbone.Interface(addr_width=0, data_width=8)
-        self.bus.memory_map = memory.MemoryMap(addr_width=1, data_width=8)
-
-
-    def elaborate(self, platform):
-        m = Module()
-
-        # Create our UART transmitter, and connect it directly to our
-        # wishbone bus.
-        m.submodules.tx = tx = UARTTransmitter(divisor=self.divisor)
-        m.d.comb += [
-            tx.stream.valid    .eq(self.bus.cyc & self.bus.stb & self.bus.we),
-            tx.stream.payload  .eq(self.bus.dat_w),
-
-            self.bus.ack.eq(tx.stream.ready),
-            self.tx.eq(tx.tx)
-        ]
-        return m
-
-
 class UARTMultibyteTransmitter(Elaboratable):
     """ UART transmitter capable of sending wide words.
 

pyproject.toml

@@ -10,16 +10,14 @@ authors = [
 ]
 description = "Amaranth HDL framework for FPGA-based USB solutions"
 readme = "README.md"
-requires-python = ">=3.8,<4.0"
+requires-python = "~=3.8"
 dependencies = [
     "apollo-fpga>=0.0.5",
     "libusb1>1.9.2",
     "pyserial>=3.5",
     "pyusb>1.1.1",
     "pyvcd>=0.2.4",
-    "ziglang>0.8.0",
-    "amaranth @ git+https://github.com/amaranth-lang/amaranth",
-    "amaranth-soc @ git+https://github.com/amaranth-lang/amaranth-soc.git@main",
+    "amaranth~=0.4.0",
     "amaranth-boards @ git+https://github.com/amaranth-lang/amaranth-boards.git@main",
     "usb-protocol @ git+https://github.com/usb-tools/python-usb-protocol",
 ]
@@ -28,8 +26,6 @@ dependencies = [
 dev = [
     "prompt-toolkit>3.0.16",
     "tox>3.22.0",
-    "minerva @ git+https://github.com/lambdaconcept/minerva.git",
-    "amaranth-stdio @ git+https://github.com/amaranth-lang/amaranth-stdio.git@main",
 ]
 
 [tool.setuptools.packages.find]

requirements_test.txt

@@ -1,7 +1,6 @@
 tox
 pyusb
-git+https://github.com/amaranth-lang/amaranth
--e git+https://github.com/amaranth-lang/amaranth-soc.git#egg=amaranth-soc
+amaranth~=0.4.0
 -e git+https://github.com/amaranth-lang/amaranth-boards.git#egg=amaranth_boards
 -e git+https://github.com/usb-tools/python-usb-protocol.git#egg=usb_protocol
 pyvcd