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SystemC to Verilog Synthesizable Subset Translator
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freecores/sc2v
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/* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Library General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ Authors: Pablo Huerta ([email protected]) Javier Castillo ([email protected]) Contributors: David Moloney Harald Devos Chris Stratford INSTRUCTIONS OF USE: 1- Compiling the sources: The sc2v translator is based on lex and yacc tools. You need lex and yacc installed before trying to compile sc2v. For compiling the sources just type "make" under the directory you unzipped the fonts. It will generate three executables: sc2v_step1 and sc2v_step2 sc2v_step3. 2- Translating an SystemC module: To translate use sc2v.sh script in the /bin directory just writting sc2v.sh module_name 3- Format and restrictions of the SystemC files: - Each module must have a .h file with the declarations of ports, signals, and processes, and there must exist a .cpp file with the code of the processes. - For writing to a port or a signal you must ALWAYS use the .write() method. -Macros not fully supported. -Only data types: bool, sc_int, sc_bigint, sc_uint and sc_biguint are supported. -No global variables supported. 4- Known bugs -The usage of macros and defines may cause some errors. 5- For testing the application we recommend to use the systemcdes,systecaes and systemcmd5 cores, available at www.opencores.org. TODO: - Repair all known bugs. - Make macros fully supported.
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