z80 codegen wip

floooh · Dec 31, 2024 · 0003f7c · 0003f7c
1 parent 96a7835
commit 0003f7c
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Showing 2 changed files with 24 additions and 19 deletions.
diff --git a/chips/z80.h b/chips/z80.h
@@ -1022,43 +1022,29 @@ uint64_t z80_tick(z80_t* cpu, uint64_t pins) {
         // <% decoder
         // %>
         //=== shared fetch machine cycle for non-DD/FD-prefixed ops
-        // M1/T2: load opcode from data bus
         case Z80_M1_T2: _wait(); cpu->opcode = _gd(); goto step_next;
-        // M1/T3: refresh cycle
         case Z80_M1_T3: pins = _z80_refresh(cpu, pins); goto step_next;
-        // M1/T4: branch to instruction 'payload'
         case Z80_M1_T4:
             cpu->step = cpu->opcode;
             cpu->addr = cpu->hl;
             goto step_to;
         //=== shared fetch machine cycle for DD/FD-prefixed ops
-        // M1/T2: load opcode from data bus
         case Z80_DDFD_M1_T2: _wait(); cpu->opcode = _gd(); goto step_next;
-        // M1/T3: refresh cycle
         case Z80_DDFD_M1_T3: pins = _z80_refresh(cpu, pins); goto step_next;
-        // M1/T4: branch to instruction 'payload'
         case Z80_DDFD_M1_T4:
-            // FIXME: if indirect_table[cpu->opcode] => DDFD_D_T1 else cpu->opcode
             cpu->step = _z80_indirect_table[cpu->opcode] ? Z80_DDFD_D_T1 : cpu->opcode;
             cpu->addr = cpu->hlx[cpu->hlx_idx].hl;
             goto step_to;
         //=== optional d-loading cycle for (IX+d), (IY+d)
-        //--- mread
         case Z80_DDFD_D_T1: goto step_next;
-        case Z80_DDFD_D_T2: _wait();_mread(cpu->pc++); goto step_next;
+        case Z80_DDFD_D_T2: _wait(); _mread(cpu->pc++); goto step_next;
         case Z80_DDFD_D_T3: cpu->addr += (int8_t)_gd(); cpu->wz = cpu->addr; goto step_next;
         //--- special case LD (IX/IY+d),n or filler ticks
         case Z80_DDFD_D_T4: goto step_next;
         case Z80_DDFD_D_T5: if (cpu->opcode == 0x36) { _wait();_mread(cpu->pc++); }; goto step_next;
         case Z80_DDFD_D_T6: if (cpu->opcode == 0x36) { cpu->dlatch = _gd(); }; goto step_next;
         case Z80_DDFD_D_T7: goto step_next;
-        case Z80_DDFD_D_T8:
-            if (cpu->opcode == 0x36) {
-                cpu->step = Z80_DDFD_LDHLN_WR_T1;
-            } else {
-                cpu->step = cpu->opcode;
-            }
-            goto step_to;
+        case Z80_DDFD_D_T8: cpu->step = (cpu->opcode==0x36) ? Z80_DDFD_LDHLN_WR_T1 : cpu->opcode; goto step_to;
         //--- special case LD (IX/IY+d),n write mcycle
         case Z80_DDFD_LDHLN_WR_T1: goto step_next;
         case Z80_DDFD_LDHLN_WR_T2: _wait(); _mwrite(cpu->addr,cpu->dlatch); goto step_next;

diff --git a/codegen/z80_gen.py b/codegen/z80_gen.py
@@ -206,6 +206,13 @@ def find_opdesc(name):
     err(f"opdesc not found for '{name}'")
     return None
 
+def find_op(name):
+    for op in OPS:
+        if op.name == name:
+            return op
+    err(f"op not found for '{name}'")
+    return None
+
 def stampout_mcycle_items(mcycle_items, y, z, p, q):
     res = {}
     for key,val in mcycle_items.items():
@@ -398,7 +405,7 @@ def add_fetch(action):
 #     return res
 
 def extra_step_defines_string(max_step):
-    extra_steps = [
+    manual_steps = [
         "M1_T2",
         "M1_T3",
         "M1_T4",
@@ -423,9 +430,21 @@ def extra_step_defines_string(max_step):
     ]
     res = ''
     step_index = max_step
-    for step in extra_steps:
-        res += f'#define Z80_{step} {step_index}\n'
+    for step_name in manual_steps:
+        res += f'#define Z80_{step_name} {step_index}\n'
         step_index += 1
+    special_steps = {
+        'cb': 'CB_STEP',
+        'cbhl': 'CBHL_STEP',
+        'ddfdcb': 'DDFDCB_STEP',
+        'int_im0': 'INT_IM0_STEP',
+        'int_im1': 'INT_IM1_STEP',
+        'int_im2': 'INT_IM2_STEP',
+        'nmi': 'NMI_STEP',
+    }
+    for op_name, step_name in special_steps.items():
+        op = find_op(op_name)
+        res += f'#define Z80_{step_name} {op.extra_step_index}\n'
     return res
 
 def write_result(decoder_output):