Patch the RTC_CNTL and RTC_IO peripherals of the ESP32-S2/S3's UL…

…P cores (#185)

* Patch the `RTC_CNTL` and `RTC_IO` peripherals of the ESP32-S2/S3's ULP core

* Regenerate PACs

esp32s2-ulp/src/rtc_io/rtc_gpio_enable.rs → esp32s2-ulp/src/rtc_io/enable.rs

@@ -1,7 +1,7 @@
-#[doc = "Register `RTC_GPIO_ENABLE` reader"]
-pub type R = crate::R<RTC_GPIO_ENABLE_SPEC>;
-#[doc = "Register `RTC_GPIO_ENABLE` writer"]
-pub type W = crate::W<RTC_GPIO_ENABLE_SPEC>;
+#[doc = "Register `ENABLE` reader"]
+pub type R = crate::R<ENABLE_SPEC>;
+#[doc = "Register `ENABLE` writer"]
+pub type W = crate::W<ENABLE_SPEC>;
 #[doc = "Field `REG_RTCIO_REG_GPIO_ENABLE` reader - GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output."]
 pub type REG_RTCIO_REG_GPIO_ENABLE_R = crate::FieldReader<u32>;
 #[doc = "Field `REG_RTCIO_REG_GPIO_ENABLE` writer - GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output."]
@@ -16,7 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("RTC_GPIO_ENABLE")
+        f.debug_struct("ENABLE")
             .field(
                 "reg_rtcio_reg_gpio_enable",
                 &format_args!("{}", self.reg_rtcio_reg_gpio_enable().bits()),
@@ -25,7 +25,7 @@ impl core::fmt::Debug for R {
     }
 }
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_SPEC> {
+impl core::fmt::Debug for crate::generic::Reg<ENABLE_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         core::fmt::Debug::fmt(&self.read(), f)
     }
@@ -34,9 +34,7 @@ impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output."]
     #[inline(always)]
     #[must_use]
-    pub fn reg_rtcio_reg_gpio_enable(
-        &mut self,
-    ) -> REG_RTCIO_REG_GPIO_ENABLE_W<RTC_GPIO_ENABLE_SPEC> {
+    pub fn reg_rtcio_reg_gpio_enable(&mut self) -> REG_RTCIO_REG_GPIO_ENABLE_W<ENABLE_SPEC> {
         REG_RTCIO_REG_GPIO_ENABLE_W::new(self, 10)
     }
     #[doc = r" Writes raw bits to the register."]
@@ -50,19 +48,19 @@ impl W {
         self
     }
 }
-#[doc = "RTC GPIO output enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct RTC_GPIO_ENABLE_SPEC;
-impl crate::RegisterSpec for RTC_GPIO_ENABLE_SPEC {
+#[doc = "RTC GPIO output enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ENABLE_SPEC;
+impl crate::RegisterSpec for ENABLE_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [`rtc_gpio_enable::R`](R) reader structure"]
-impl crate::Readable for RTC_GPIO_ENABLE_SPEC {}
-#[doc = "`write(|w| ..)` method takes [`rtc_gpio_enable::W`](W) writer structure"]
-impl crate::Writable for RTC_GPIO_ENABLE_SPEC {
+#[doc = "`read()` method returns [`enable::R`](R) reader structure"]
+impl crate::Readable for ENABLE_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"]
+impl crate::Writable for ENABLE_SPEC {
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }
-#[doc = "`reset()` method sets RTC_GPIO_ENABLE to value 0"]
-impl crate::Resettable for RTC_GPIO_ENABLE_SPEC {
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for ENABLE_SPEC {
     const RESET_VALUE: Self::Ux = 0;
 }

esp32s2-ulp/src/rtc_io/rtc_gpio_enable_w1tc.rs → esp32s2-ulp/src/rtc_io/enable_w1tc.rs

@@ -1,9 +1,9 @@
-#[doc = "Register `RTC_GPIO_ENABLE_W1TC` writer"]
-pub type W = crate::W<RTC_GPIO_ENABLE_W1TC_SPEC>;
+#[doc = "Register `ENABLE_W1TC` writer"]
+pub type W = crate::W<ENABLE_W1TC_SPEC>;
 #[doc = "Field `REG_RTCIO_REG_GPIO_ENABLE_W1TC` writer - GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG."]
 pub type REG_RTCIO_REG_GPIO_ENABLE_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_W1TC_SPEC> {
+impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TC_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "(not readable)")
     }
@@ -14,7 +14,7 @@ impl W {
     #[must_use]
     pub fn reg_rtcio_reg_gpio_enable_w1tc(
         &mut self,
-    ) -> REG_RTCIO_REG_GPIO_ENABLE_W1TC_W<RTC_GPIO_ENABLE_W1TC_SPEC> {
+    ) -> REG_RTCIO_REG_GPIO_ENABLE_W1TC_W<ENABLE_W1TC_SPEC> {
         REG_RTCIO_REG_GPIO_ENABLE_W1TC_W::new(self, 10)
     }
     #[doc = r" Writes raw bits to the register."]
@@ -28,17 +28,17 @@ impl W {
         self
     }
 }
-#[doc = "RTC GPIO output enable bit clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_enable_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct RTC_GPIO_ENABLE_W1TC_SPEC;
-impl crate::RegisterSpec for RTC_GPIO_ENABLE_W1TC_SPEC {
+#[doc = "RTC GPIO output enable bit clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ENABLE_W1TC_SPEC;
+impl crate::RegisterSpec for ENABLE_W1TC_SPEC {
     type Ux = u32;
 }
-#[doc = "`write(|w| ..)` method takes [`rtc_gpio_enable_w1tc::W`](W) writer structure"]
-impl crate::Writable for RTC_GPIO_ENABLE_W1TC_SPEC {
+#[doc = "`write(|w| ..)` method takes [`enable_w1tc::W`](W) writer structure"]
+impl crate::Writable for ENABLE_W1TC_SPEC {
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }
-#[doc = "`reset()` method sets RTC_GPIO_ENABLE_W1TC to value 0"]
-impl crate::Resettable for RTC_GPIO_ENABLE_W1TC_SPEC {
+#[doc = "`reset()` method sets ENABLE_W1TC to value 0"]
+impl crate::Resettable for ENABLE_W1TC_SPEC {
     const RESET_VALUE: Self::Ux = 0;
 }

esp32s2-ulp/src/rtc_io/rtc_gpio_enable_w1ts.rs → esp32s2-ulp/src/rtc_io/enable_w1ts.rs

@@ -1,9 +1,9 @@
-#[doc = "Register `RTC_GPIO_ENABLE_W1TS` writer"]
-pub type W = crate::W<RTC_GPIO_ENABLE_W1TS_SPEC>;
+#[doc = "Register `ENABLE_W1TS` writer"]
+pub type W = crate::W<ENABLE_W1TS_SPEC>;
 #[doc = "Field `REG_RTCIO_REG_GPIO_ENABLE_W1TS` writer - GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG."]
 pub type REG_RTCIO_REG_GPIO_ENABLE_W1TS_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_ENABLE_W1TS_SPEC> {
+impl core::fmt::Debug for crate::generic::Reg<ENABLE_W1TS_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "(not readable)")
     }
@@ -14,7 +14,7 @@ impl W {
     #[must_use]
     pub fn reg_rtcio_reg_gpio_enable_w1ts(
         &mut self,
-    ) -> REG_RTCIO_REG_GPIO_ENABLE_W1TS_W<RTC_GPIO_ENABLE_W1TS_SPEC> {
+    ) -> REG_RTCIO_REG_GPIO_ENABLE_W1TS_W<ENABLE_W1TS_SPEC> {
         REG_RTCIO_REG_GPIO_ENABLE_W1TS_W::new(self, 10)
     }
     #[doc = r" Writes raw bits to the register."]
@@ -28,17 +28,17 @@ impl W {
         self
     }
 }
-#[doc = "RTC GPIO output enable bit set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_enable_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct RTC_GPIO_ENABLE_W1TS_SPEC;
-impl crate::RegisterSpec for RTC_GPIO_ENABLE_W1TS_SPEC {
+#[doc = "RTC GPIO output enable bit set register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable_w1ts::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ENABLE_W1TS_SPEC;
+impl crate::RegisterSpec for ENABLE_W1TS_SPEC {
     type Ux = u32;
 }
-#[doc = "`write(|w| ..)` method takes [`rtc_gpio_enable_w1ts::W`](W) writer structure"]
-impl crate::Writable for RTC_GPIO_ENABLE_W1TS_SPEC {
+#[doc = "`write(|w| ..)` method takes [`enable_w1ts::W`](W) writer structure"]
+impl crate::Writable for ENABLE_W1TS_SPEC {
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }
-#[doc = "`reset()` method sets RTC_GPIO_ENABLE_W1TS to value 0"]
-impl crate::Resettable for RTC_GPIO_ENABLE_W1TS_SPEC {
+#[doc = "`reset()` method sets ENABLE_W1TS to value 0"]
+impl crate::Resettable for ENABLE_W1TS_SPEC {
     const RESET_VALUE: Self::Ux = 0;
 }

esp32s2-ulp/src/rtc_io/rtc_gpio_in.rs → esp32s2-ulp/src/rtc_io/in_.rs

@@ -1,5 +1,5 @@
-#[doc = "Register `RTC_GPIO_IN` reader"]
-pub type R = crate::R<RTC_GPIO_IN_SPEC>;
+#[doc = "Register `IN` reader"]
+pub type R = crate::R<IN_SPEC>;
 #[doc = "Field `GPIO_IN_NEXT` reader - GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level."]
 pub type GPIO_IN_NEXT_R = crate::FieldReader<u32>;
 impl R {
@@ -12,7 +12,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("RTC_GPIO_IN")
+        f.debug_struct("IN")
             .field(
                 "gpio_in_next",
                 &format_args!("{}", self.gpio_in_next().bits()),
@@ -21,19 +21,19 @@ impl core::fmt::Debug for R {
     }
 }
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_IN_SPEC> {
+impl core::fmt::Debug for crate::generic::Reg<IN_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         core::fmt::Debug::fmt(&self.read(), f)
     }
 }
-#[doc = "RTC GPIO input register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_in::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct RTC_GPIO_IN_SPEC;
-impl crate::RegisterSpec for RTC_GPIO_IN_SPEC {
+#[doc = "RTC GPIO input register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IN_SPEC;
+impl crate::RegisterSpec for IN_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [`rtc_gpio_in::R`](R) reader structure"]
-impl crate::Readable for RTC_GPIO_IN_SPEC {}
-#[doc = "`reset()` method sets RTC_GPIO_IN to value 0"]
-impl crate::Resettable for RTC_GPIO_IN_SPEC {
+#[doc = "`read()` method returns [`in_::R`](R) reader structure"]
+impl crate::Readable for IN_SPEC {}
+#[doc = "`reset()` method sets IN to value 0"]
+impl crate::Resettable for IN_SPEC {
     const RESET_VALUE: Self::Ux = 0;
 }

esp32s2-ulp/src/rtc_io/rtc_gpio_out.rs → esp32s2-ulp/src/rtc_io/out.rs

@@ -1,7 +1,7 @@
-#[doc = "Register `RTC_GPIO_OUT` reader"]
-pub type R = crate::R<RTC_GPIO_OUT_SPEC>;
-#[doc = "Register `RTC_GPIO_OUT` writer"]
-pub type W = crate::W<RTC_GPIO_OUT_SPEC>;
+#[doc = "Register `OUT` reader"]
+pub type R = crate::R<OUT_SPEC>;
+#[doc = "Register `OUT` writer"]
+pub type W = crate::W<OUT_SPEC>;
 #[doc = "Field `GPIO_OUT_DATA` reader - GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc."]
 pub type GPIO_OUT_DATA_R = crate::FieldReader<u32>;
 #[doc = "Field `GPIO_OUT_DATA` writer - GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc."]
@@ -16,7 +16,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("RTC_GPIO_OUT")
+        f.debug_struct("OUT")
             .field(
                 "gpio_out_data",
                 &format_args!("{}", self.gpio_out_data().bits()),
@@ -25,7 +25,7 @@ impl core::fmt::Debug for R {
     }
 }
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_SPEC> {
+impl core::fmt::Debug for crate::generic::Reg<OUT_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         core::fmt::Debug::fmt(&self.read(), f)
     }
@@ -34,7 +34,7 @@ impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc."]
     #[inline(always)]
     #[must_use]
-    pub fn gpio_out_data(&mut self) -> GPIO_OUT_DATA_W<RTC_GPIO_OUT_SPEC> {
+    pub fn gpio_out_data(&mut self) -> GPIO_OUT_DATA_W<OUT_SPEC> {
         GPIO_OUT_DATA_W::new(self, 10)
     }
     #[doc = r" Writes raw bits to the register."]
@@ -48,19 +48,19 @@ impl W {
         self
     }
 }
-#[doc = "RTC GPIO output register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rtc_gpio_out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct RTC_GPIO_OUT_SPEC;
-impl crate::RegisterSpec for RTC_GPIO_OUT_SPEC {
+#[doc = "RTC GPIO output register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_SPEC;
+impl crate::RegisterSpec for OUT_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [`rtc_gpio_out::R`](R) reader structure"]
-impl crate::Readable for RTC_GPIO_OUT_SPEC {}
-#[doc = "`write(|w| ..)` method takes [`rtc_gpio_out::W`](W) writer structure"]
-impl crate::Writable for RTC_GPIO_OUT_SPEC {
+#[doc = "`read()` method returns [`out::R`](R) reader structure"]
+impl crate::Readable for OUT_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"]
+impl crate::Writable for OUT_SPEC {
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }
-#[doc = "`reset()` method sets RTC_GPIO_OUT to value 0"]
-impl crate::Resettable for RTC_GPIO_OUT_SPEC {
+#[doc = "`reset()` method sets OUT to value 0"]
+impl crate::Resettable for OUT_SPEC {
     const RESET_VALUE: Self::Ux = 0;
 }

esp32s2-ulp/src/rtc_io/rtc_gpio_out_w1tc.rs → esp32s2-ulp/src/rtc_io/out_w1tc.rs

@@ -1,9 +1,9 @@
-#[doc = "Register `RTC_GPIO_OUT_W1TC` writer"]
-pub type W = crate::W<RTC_GPIO_OUT_W1TC_SPEC>;
-#[doc = "Field `GPIO_OUT_DATA_W1TC` writer - GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG."]
-pub type GPIO_OUT_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
+#[doc = "Register `OUT_W1TC` writer"]
+pub type W = crate::W<OUT_W1TC_SPEC>;
+#[doc = "Field `OUT_DATA_W1TC` writer - GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG."]
+pub type OUT_DATA_W1TC_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>;
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<RTC_GPIO_OUT_W1TC_SPEC> {
+impl core::fmt::Debug for crate::generic::Reg<OUT_W1TC_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "(not readable)")
     }
@@ -12,8 +12,8 @@ impl W {
     #[doc = "Bits 10:31 - GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG."]
     #[inline(always)]
     #[must_use]
-    pub fn gpio_out_data_w1tc(&mut self) -> GPIO_OUT_DATA_W1TC_W<RTC_GPIO_OUT_W1TC_SPEC> {
-        GPIO_OUT_DATA_W1TC_W::new(self, 10)
+    pub fn out_data_w1tc(&mut self) -> OUT_DATA_W1TC_W<OUT_W1TC_SPEC> {
+        OUT_DATA_W1TC_W::new(self, 10)
     }
     #[doc = r" Writes raw bits to the register."]
     #[doc = r""]
@@ -26,17 +26,17 @@ impl W {
         self
     }
 }
-#[doc = "RTC GPIO output bit clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rtc_gpio_out_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct RTC_GPIO_OUT_W1TC_SPEC;
-impl crate::RegisterSpec for RTC_GPIO_OUT_W1TC_SPEC {
+#[doc = "RTC GPIO output bit clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_w1tc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct OUT_W1TC_SPEC;
+impl crate::RegisterSpec for OUT_W1TC_SPEC {
     type Ux = u32;
 }
-#[doc = "`write(|w| ..)` method takes [`rtc_gpio_out_w1tc::W`](W) writer structure"]
-impl crate::Writable for RTC_GPIO_OUT_W1TC_SPEC {
+#[doc = "`write(|w| ..)` method takes [`out_w1tc::W`](W) writer structure"]
+impl crate::Writable for OUT_W1TC_SPEC {
     const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }
-#[doc = "`reset()` method sets RTC_GPIO_OUT_W1TC to value 0"]
-impl crate::Resettable for RTC_GPIO_OUT_W1TC_SPEC {
+#[doc = "`reset()` method sets OUT_W1TC to value 0"]
+impl crate::Resettable for OUT_W1TC_SPEC {
     const RESET_VALUE: Self::Ux = 0;
 }