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feat: experimental LEC to resizer steps #576

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feat: experimental LEC to resizer steps #576

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@donn donn commented Oct 9, 2024

Steps

  • OpenROAD.*

    • All steps now output both a powered AND an unpowered netlist with only logical cells.
    • Cells for logical netlists are now filtered using LEF classes and not input variables.
  • OpenROAD.Resizer*, OpenROAD.Repair*

    • New experimental variable RSZ_LEC, which attempts to verify that resizing did not alter the functionality of the circuit using EQY.

Misc. Enhancements/Bugfixes

  • New DesignFormat: NETLIST_NO_PHYSICAL_CELLS (unpowered)
    • Heads up: We're going to rename those to simply "logical" in OpenLane 3.

Tool Updates

  • Update nix-eda to ff3ca89
    • Updates Yosys to 0.46

## Steps

* `OpenROAD.*`
  * All steps now output both a powered AND an unpowered netlist with only logical cells.
  * Cells for logical netlists are now filtered using LEF classes and not input variables.

* `OpenROAD.Resizer*`, `OpenROAD.Repair*`
  * New experimental variable `RSZ_LEC`, which attempts to verify that resizing did not alter the functionality of the circuit using EQY.

## Misc. Enhancements/Bugfixes

* New `DesignFormat`: `NETLIST_NO_PHYSICAL_CELLS` (unpowered)
  * **Heads up**: We're going to rename those to simply "logical" in OpenLane 3.

## Tool Updates

* Update `nix-eda` to `ff3ca89`
  * Updates Yosys to 0.46
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Metric comparisons are in beta. Please report bugs under the issues tab.

To create this report yourself, grab the metrics artifact from the CI run, extract them, and invoke python3 -m openlane.common.metrics compare-remote current --branch dev --table-verbosity ALL --table-out ./tables_all.md.

  • Changes to critical metrics were detected in the following designs:
    • gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
    • sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE

Full tables ► https://gist.github.com/openlane-bot/4f9afc12c30a460f8e7e574ad1e83c18

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