[Course] Add slides for all courses with exam questions (#35)

* Fixed the typos.

* feat: course no.2 information representation

* feat: course no.3 memory

* feat: exam questions ofr course no.3

* Modified course 2 - first modification

* Modified course 2 - reset text from number.tex

* wip: course no. 4

* feat: course no.4  add riple carry and carry lookahead

* feat: course no.4

* fix: some grammar for course no. 4

* fix: grammar for course no. 3

* fix: improve course no. 3

* fix: improve course no. 4

* fix: cousre no.4 small changes.

* fix: delete education hub linter

* feat: course no. 5

* fix: exam questions for course no.5

* feat: course no. 6

* feat: course no. 7

* wip: course no. 8

* feat: course no. 8

* feat: course no. 9

.devcontainer/devcontainer.json

@@ -1,16 +1,37 @@
 {
-	"name": "Vivado Slim Dev",
-	"image": "gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0",
-	"runArgs": [
-		"--rm",
-		"--privileged"
-	],
-	"mounts": ["type=bind,source=/dev,target=/dev"],
+	// Lab development container configuration Vivado Slim Dev
+	// "name": "Vivado Slim Dev",
+	// "image": "gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0",
+	// Open source toolchain container for VPL
+	// "name": "Icarus Verilog",
+	// "build": {
+	// 	"dockerfile": "open.Dockerfile",
+	// },
+	// Latex container for course materials
+	"name": "Latex",
+	"build": {
+		"dockerfile": "latex.Dockerfile",
+	},
 	"customizations": {
 		"vscode": {
 			"extensions": [
-				"mshr-h.veriloghdl"
+				"GitHub.vscode-pull-request-github",
+				"james-yu.latex-workshop",
+				"GitHub.copilot",
+				"Bito.Bito"
 			]
 		}
-	}
+	},
+	"runArgs": [
+		"--rm",
+		"--privileged"
+	],
+	// "mounts": ["type=bind,source=/dev,target=/dev"],
+	// "customizations": {
+	// 	"vscode": {
+	// 		"extensions": [
+	// 			"mshr-h.veriloghdl"
+	// 		]
+	// 	}
+	// }
 }

slides/.devcontainer/Dockerfile → .devcontainer/latex.Dockerfile

@@ -2,9 +2,9 @@
 FROM ubuntu:22.04
 
 # LABEL about the custom image
-LABEL maintainer="[email protected]"
+LABEL maintainer="[email protected]"
 LABEL version="0.1"
-LABEL description="Latex environment for SBIP"
+LABEL description="Latex environment for AC course"
 
 # Disable Prompt During Packages Installation
 ARG DEBIAN_FRONTEND=noninteractive
@@ -25,4 +25,6 @@ RUN apt-get update && \
 
 #RUN wget http://beta.plantuml.net/batikAndFop.zip -P ./plantuml && wget http://beta.plantuml.net/plantuml-jlatexmath.zip -P ./plantuml
 # RUN unzip -o ./plantuml/batikAndFop.zip -d ./plantuml && unzip -o ./plantuml/plantuml-jlatexmath.zip -d ./plantuml
-# RUN java -Djava.awt.headless=true -jar ./plantuml/plantuml-1.2023.11.jar ./diagrams/architecturev2.uml -o ./plantuml -tpdf
+# RUN java -Djava.awt.headless=true -jar ./plantuml/plantuml-1.2023.11.jar ./diagrams/architecturev2.uml -o ./plantuml -tpdf
+# for latex coding with minted
+RUN pip3 install Pygments

.vscode/settings.json

@@ -0,0 +1,44 @@
+{
+    "latex-workshop.latex.outDir": "out",
+    "latex-workshop.synctex.afterBuild.enabled": true,
+    "latex-workshop.view.pdf.viewer": "tab",
+    "latex-workshop.latex.build.forceRecipeUsage": false,
+    "latex-workshop.latex.search.rootFiles.include": ["**/courses/5/main.tex"], // Change this to the path of your main tex file
+    "latex-workshop.view.pdf.internal.synctex.keybinding": "double-click",
+    "latex-workshop.latex.autoClean.run": "onBuilt",
+    "latex-workshop.latex.autoBuild.run": "onSave",
+    "latex-workshop.latex.tools": [
+      {
+        "name": "latexmk",
+        "command": "latexmk",
+        "args": [
+          "-synctex=1",
+          "-interaction=nonstopmode",
+          "-file-line-error",
+          "--shell-escape",
+          "-pdf",
+          "-outdir=%OUTDIR%",
+          "%DOC%"
+        ]
+      },
+      {
+        "name": "pdflatex",
+        "command": "pdflatex",
+        "args": [
+          "--shell-escape",
+          "-synctex=1",
+          "-interaction=nonstopmode",
+          "-file-line-error",
+          "%DOC%"
+        ]
+      },
+      {
+        "name": "bibtex",
+        "command": "bibtex",
+        "args": [
+          "%DOCFILE%"
+        ],
+        "env": {}
+      }
+    ],
+}

slides/courses/5/architecture.tex

@@ -0,0 +1,8 @@
+\begin{frame}
+    \frametitle{Architecture}
+    \begin{figure}
+        \centering
+        \includegraphics[height=0.7\textheight]{media/architecture.png}
+        \caption{Architecture}
+    \end{figure}
+\end{frame}

slides/courses/5/components.tex

@@ -0,0 +1,166 @@
+\begin{frame}
+    \frametitle{Register}
+    \begin{circuitikz}
+        \draw
+        (0,0) node[draw, minimum width=2cm, minimum height=3cm] (chip) {Register}
+        (chip.west) ++(-0.5,1) node[left] {Data Input (DI)} -- (chip.west |- 0,1)
+        (chip.west) ++(-0.5,0) node[left] {Write Enable (WE)} -- (chip.west |- 0,0)
+        (chip.west) ++(-0.5,-1) node[left] {Output Enable (OE)} -- (chip.west |- 0,-1)
+        (chip.east) ++(0.5,0) node[right] {Data Output (DO)} -- (chip.east |- 0,0);
+    \end{circuitikz}
+
+    \note{
+    }
+\end{frame}
+
+\begin{frame}
+    \frametitle{General Purpose Registers (GR)}
+    \begin{table}[]
+        \begin{tabular}{|l|l|l|}
+            \hline
+            \textbf{Register} & \textbf{Acronym} & \textbf{Size} \\ \hline
+            Register A & RA & 16-bit \\ \hline
+            Register B & RB & 16-bit \\ \hline
+            Register C & RC & 16-bit \\ \hline
+            Stack Pointer Register & SP & 16-bit \\ \hline
+            Index Register A & XA & 16-bit \\ \hline
+            Index Register B & XB & 16-bit \\ \hline
+            Base Address A & BA & 16-bit \\ \hline
+            Base Address B & BB & 16-bit \\ \hline
+        \end{tabular}
+    \end{table}
+    \note{
+    }
+\end{frame}
+
+
+\begin{frame}
+    \frametitle{Registers File (RF)}
+
+    \begin{circuitikz}
+        % Demux
+        \draw
+        (0,0) node[muxdemux, muxdemux def={Lh=4, Rh=8, NL=3, NR=8, NT=0, NB=3, w=2,
+        square pins=1}] (C) at (0,0) {I};
+        % Inputs
+    \node[left, font=\tiny] at (C.lpin 1) {DI};
+    \node[left, font=\tiny] at (C.lpin 2) {WE};
+    \node[left, font=\tiny] at (C.lpin 3) {OE};
+
+    % Outputs
+    \node[above, font=\tiny] at (C.rpin 1) {RA};
+    \node[right, font=\tiny] at (C.rpin 2) {RB};
+    \node[right, font=\tiny] at (C.rpin 3) {RC};
+    \node[right, font=\tiny] at (C.rpin 4) {SP};
+    \node[right, font=\tiny] at (C.rpin 5) {XA};
+    \node[right, font=\tiny] at (C.rpin 6) {XB};
+    \node[right, font=\tiny] at (C.rpin 7) {BA};
+    \node[right, font=\tiny] at (C.rpin 8) {BB};
+    \node[below, font=\tiny] at (C.bpin 1) {Register Address (REG)};
+
+    % Split RA output into 3 connections
+    \draw (C.rpin 1) -- ++(1.0,0) coordinate (split) 
+    (split) |- ++(1,1.0) node[right, font=\tiny] {DI}
+    (split) |- ++(1,-1.0) node[right, font=\tiny] {WE}
+    (split) -- ++(1,0) node[right, font=\tiny] {OE};
+
+    % Connect to another component
+    \draw (split) -- ++(1,0) node[draw, minimum width=2cm, minimum height=3cm, anchor=west] (chip) {RA}
+    (chip.east) node[left, font=\tiny] {DO}
+    (chip.east) |- ++(1,0.0) node[muxdemux, muxdemux def={Lh=8, Rh=1, NL=8, NR=1, NT=0, NB=3, w=2,
+    square pins=1}] (D) at (6.5,0) {O};
+    % Inputs
+    \node[above, font=\tiny] at (D.lpin 1) {RA};
+    \node[left, font=\tiny] at (D.lpin 2) {RB};
+    \node[left, font=\tiny] at (D.lpin 3) {RC};
+    \node[left, font=\tiny] at (D.lpin 4) {SP};
+    \node[left, font=\tiny] at (D.lpin 5) {XA};
+    \node[left, font=\tiny] at (D.lpin 6) {XB};
+    \node[left, font=\tiny] at (D.lpin 7) {BA};
+    \node[left, font=\tiny] at (D.lpin 8) {BB};
+    \node[below, font=\tiny] at (D.bpin 1) {Register Address (REG)};
+
+    % Outputs
+    \node[above, font=\tiny] at (D.rpin 1) {DO};
+
+    \end{circuitikz}
+\end{frame}
+
+\begin{frame}
+    \frametitle{Special Purpose Registers}
+    \begin{table}[]
+        \begin{tabular}{|l|l|l|}
+            \hline
+            \textbf{Register} & \textbf{Acronym} & \textbf{Size} \\ \hline
+            Program Counter & PC & 16-bit \\ \hline
+            Instruction Register & IR & 16-bit \\ \hline
+            Memory Address Register & MA & 16-bit \\ \hline
+            Flags Register & FR & 16-bit \\ \hline
+            Operand Register 1 & T1 & 16-bit \\ \hline
+            Operand Register 2 & T2 & 16-bit \\ \hline
+            Input/Output Addressing Register & IOA & 16-bit \\ \hline
+        \end{tabular}
+    \end{table}
+\end{frame}
+
+\begin{frame}
+    \frametitle{Memory (M)}
+    \begin{itemize}
+        \item Address width: 16-bit
+        \item Data width: 16-bit
+    \end{itemize}
+    \begin{circuitikz}
+        \draw
+        (0,0) node[draw, minimum width=2cm, minimum height=4cm] (chip) {Memory}
+        (chip.west) ++(-0.5,1) node[left] {Address (MA)} -- (chip.west |- 0,1)
+        (chip.west) ++(-0.5,0.5) node[left] {Memory Input (MI)} -- (chip.west |- 0,0.5)
+        (chip.west) ++(-0.5,-0.5) node[left] {Write Enable (WE)} -- (chip.west |- 0,-0.5)
+        (chip.west) ++(-0.5,-1) node[left] {Output Enable (OE)} -- (chip.west |- 0,-1)
+        (chip.east) ++(0.5,0) node[right] {Memory Output (MO)} -- (chip.east |- 0,0);
+    \end{circuitikz}
+
+\end{frame}
+
+\begin{frame}
+    \frametitle{Arithmetic Logic Unit (ALU)}
+    \begin{circuitikz}
+        \draw
+        (0,0) node[muxdemux, muxdemux def={Lh=7, NL=2, Rh=4, NR=2, NB=1, NT=2, w=4,
+        inset w=1, inset Lh=2, inset Rh=0, square pins=1}] (chip) {ALU}
+        % Inputs
+        (chip.lpin 1) node[left] {Operand 1 (T1)}
+        (chip.lpin 2) node[left] {Operand 2 (T2)}
+        (chip.bpin 1) node[below] {Operation (OP)}
+        (chip.tpin 1) node[left] {Carry In (CI)}
+        (chip.tpin 2) node[right] {Output Enable (OE)}
+
+        % Outputs
+        (chip.rpin 1) node[right] {Result (R)}
+        (chip.rpin 2) node[right] {Flags (FR)};
+
+    \end{circuitikz}
+\end{frame}
+
+\begin{frame}
+    \frametitle{Internal Bus}
+    \begin{table}[]
+        \resizebox{\textwidth}{!}{%
+        \begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|}
+            \hline
+            \textbf{Source} & \textbf{GR} & \textbf{M} & \textbf{T1} & \textbf{T2} & \textbf{IR} & \textbf{PC} & \textbf{IO} & \textbf{IOA} & \textbf{ALU} & \textbf{MA} & \textbf{FR} \\ \hline
+            \textbf{GR} & X & X & X & X & - & X & X & - & - & X & - \\ \hline
+            \textbf{M} & X & X & X & X & X & X & X & - & - & X & X \\ \hline
+            \textbf{T1} & - & - & - & - & - & - & - & - & X & - & - \\ \hline
+            \textbf{T2} & - & - & - & - & - & - & - & - & X & - & - \\ \hline
+            \textbf{IR} & - & - & - & - & - & - & - & X & - & - & - \\ \hline
+            \textbf{PC} & X & X & - & - & - & X & - & - & - & X & - \\ \hline
+            \textbf{IO} & X & X & - & - & - & - & - & - & - & - & - \\ \hline
+            \textbf{IOA} & - & - & - & - & - & - & X & - & - & - & - \\ \hline
+            \textbf{ALU} & X & X & X & X & - & X & - & - & - & X & X \\ \hline
+            \textbf{MA} & - & - & - & - & - & - & - & - & - & - & - \\ \hline
+            \textbf{FR} & - & X & - & - & - & - & - & - & - & - & - \\ \hline
+        \end{tabular}
+        }
+    \end{table}
+
+\end{frame}