An opinion

[claubersouza]

The main proposal for my doctoral dissertation is to be able to select a certain algorithm snippet to generate a custom ISA. The idea is to create a VSCode extension to automate the process.

The process steps:

Code Analysis

The objective of this section is to develop or integrate a code analysis mechanism that can identify C language code patterns and extract relevant information for the creation of ISA instructions. This may include identifying mathematical operations, flow control, memory access, etc.

1. The "Code Analysis" stage is often one of the most complex parts of projects like this. Code analysis involves understanding and interpreting source code, identifying relevant patterns and structures, isolating semantic information, and then translating that information into instructions for a custom ISA. This stage may involve:

• Lexer and Parser: Develop or use a lexical analyzer (lexer) and a syntactic analyzer (parser) to separate source code into tokens and programming structures. This is essential to identify the relevant parts of the code.

• Semantic Analysis: In addition to syntactic analysis, you will also need to perform a semantic analysis to understand the meaning of instructions and expressions in the code. This may include identifying variables, constants, operators, etc.

• Internal Representation: Develop an algorithm that will represent the extracted information in an internal structure that allows the generation of ISA instructions. This may involve creating abstract syntax trees or other suitable representation.

• Error Handling: Consider how to handle parsing errors, such as invalid or unsupported code. Developing a robust error handling mechanism is important to ensure the reliability of the extension.

• Optimization: Explore code optimization during the analysis process, identifying opportunities to improve the performance of the generated code, I believe that here will be the main contribution, developing an algorithm for optimization, being able to use machine learning to help with code analysis, especially for recognize complex patterns.

2. ISA Design: Based on code analysis, you must create an instruction design that is efficient and suitable for the identified operations. This may involve defining new instructions or adapting existing instructions.
3. Assembly Code Generation: Your extension must be able to generate assembly code corresponding to the ISA instructions you defined.
4. 4. Integration with OpenASIP: as a basis for creating the ISA, it will be necessary to integrate the extension with the tool. This may involve generating VHDL descriptions for the new processor core.
5. User Interface (UI): Develop a friendly user interface within VSCode that allows users to select code snippets and begin the ISA creation process.

Expected Final Result, automatically generate the new ISA within the VSCode IDE

I would like to know your opinion on whether my proposal is interesting.

[karihepola]

Automatic instruction set extension is definitely an interesting topic and indeed not currently supported in OpenASIP. There is some previous work on this topic. My understanding is that they use data dependecy graphs (DDGs) to find interesting operation patterns. On the other hand, it could be interesting to recognize the operation patterns in an earlier stage of the compiler flow if it is indeed possible. I am unsure what is the correct approach without further investigation. Operation pattern recognition is most likely not enough as you want to find also the hot spots in the program either via static or dynamic analysis.

What it comes to tooling, you are correct, the RISC-V features are less mature. Generating assembly with the compiler is not possible and it instead converts the custom instructions to binary directly in the compiled code. The obvious way forward is to generate the compiler backend based on the architecture definition file (ADF). This is how it is done for TTA, that has more mature features in the toolset. One could most likely reuse many parts of the backend generation code and generate the custom instruction definitions on top of the standard LLVM RISC-V backend.

The hardware generation support is more mature since it is largely shared between TTA and RISC-V. I suggest that you generate the custom instructions to the OpenASIP operation DAG format. This way you can 1) Generate the custom function units automatically without writing RTL 2) With the possible compiler improvements you can generate the compiler backend automatically when the custom operations are described in the DAG format. This is already implemented for TTA.

Your topic sounds interesting and would be a good addition to OpenASIP toolset. In general, contributions are more than welcome.

[claubersouza]

One question

The tool creates some custom pipeline when creating an custom ISA ?

[karihepola]

Yes, the tool generates the processor pipeline and custom functions units (custom operation implementations and their pipelines) based on the architecture definition file and hardware databases.