Skip to content

Commit

Permalink
covering as cap port name
Browse files Browse the repository at this point in the history
  • Loading branch information
xieyuheng committed Aug 29, 2023
1 parent 925c6ea commit 247cd65
Show file tree
Hide file tree
Showing 10 changed files with 23 additions and 21 deletions.
2 changes: 0 additions & 2 deletions TODO.md
Original file line number Diff line number Diff line change
@@ -1,7 +1,5 @@
`Cap` as special `Node` -- `Node` has optional `cap`

- with `covering` as port name

`cap` as a builtin

# articles
Expand Down
6 changes: 3 additions & 3 deletions package-lock.json

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

5 changes: 1 addition & 4 deletions src/lang/cap/connectCapInputPort.ts
Original file line number Diff line number Diff line change
Expand Up @@ -7,15 +7,14 @@ import { Port } from "../port"

export function connectCapInputPort(mod: Mod, net: Net, port: Port): Port {
const nodeName = `_cap_input_node_for_${port.name}_of_${port.node.name}`
const portName = `_cap_input_port_for_${port.name}_of_${port.node.name}`
const node = addNode(
net,
mod,
nodeName,
[
{
"@type": "PortExp",
name: portName,
name: "covering",
t: port.t,
isPrincipal: true,
},
Expand All @@ -24,8 +23,6 @@ export function connectCapInputPort(mod: Mod, net: Net, port: Port): Port {
)

const capPort = findInputPorts(net, node)[0]

connect(net, port, capPort)

return capPort
}
5 changes: 1 addition & 4 deletions src/lang/cap/connectCapOutputPort.ts
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ import { Port } from "../port"

export function connectCapOutputPort(mod: Mod, net: Net, port: Port): Port {
const nodeName = `_cap_output_node_for_${port.name}_of_${port.node.name}`
const portName = `_cap_output_port_for_${port.name}_of_${port.node.name}`
const node = addNode(
net,
mod,
Expand All @@ -16,16 +15,14 @@ export function connectCapOutputPort(mod: Mod, net: Net, port: Port): Port {
[
{
"@type": "PortExp",
name: portName,
name: "covering",
t: port.t,
isPrincipal: true,
},
],
)

const capPort = findOutputPorts(net, node)[0]

connect(net, port, capPort)

return capPort
}
3 changes: 1 addition & 2 deletions src/lang/cap/createCapOutputPortForType.ts
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@ import { Value } from "../value"

export function createCapOutputPortForType(mod: Mod, net: Net, t: Value): Port {
const nodeName = `_cap_output_node_from_type`
const portName = `_cap_output_port_from_type`
const node = addNode(
net,
mod,
Expand All @@ -16,7 +15,7 @@ export function createCapOutputPortForType(mod: Mod, net: Net, t: Value): Port {
[
{
"@type": "PortExp",
name: portName,
name: "covering",
t,
isPrincipal: true,
},
Expand Down
2 changes: 1 addition & 1 deletion tests/checking/claim-input-arity-extra.error.i.err
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
[checkWords] I expect the stack to be empty after checking.

stack length: 1
stack: [(_cap_output_node_from_type₀)-_cap_output_port_from_type!]
stack: [(_cap_output_node_from_type₀)-covering!]

Maybe this is due to extra input arity,
or lack of output arity.
Expand Down
2 changes: 1 addition & 1 deletion tests/checking/claim-output-arity-lack.error.i.err
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
[checkWords] I expect the stack to be empty after checking.

stack length: 1
stack: [(_cap_output_node_from_type₀)-_cap_output_port_from_type!]
stack: [(_cap_output_node_from_type₀)-covering!]

Maybe this is due to extra input arity,
or lack of output arity.
Expand Down
4 changes: 2 additions & 2 deletions tests/checking/rule-sign.error.i.err
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
[checkSigns] I expect the two ports to have opposite signs,
but they all have positive sign.

first port: (_cap_output_node_for_addend_of_add₁)-_cap_output_port_for_addend_of_add!
second port: (_cap_output_node_for_prev_of_add1₀)-_cap_output_port_for_prev_of_add1!
first port: (_cap_output_node_for_addend_of_add₁)-covering!
second port: (_cap_output_node_for_prev_of_add1₀)-covering!

[compose] I fail compose word.

Expand Down
11 changes: 11 additions & 0 deletions tests/module/reuqire-more-rules-3.i.out
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
net_from_port (zero₁)-value! end
net_from_port (add1₄)-value!
(add1₄)-prev value-(add1₂)
(add1₂)-prev value-(zero₃)
end
net_from_port (add1₉)-value!
(add1₉)-prev value-(add1₁₀)
(add1₁₀)-prev value-(add1₆)
(add1₆)-prev value-(add1₅)
(add1₅)-prev value-(zero₅)
end
4 changes: 2 additions & 2 deletions tests/value/input-and-output-placeholders.i.out
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
net_from_port (_cap_output_node_for_addend_of_add₁)-_cap_output_port_for_addend_of_add! end
net_from_port (_cap_input_node_for_return_of_add₁)-_cap_input_port_for_return_of_add! end
net_from_port (_cap_output_node_for_addend_of_add₁)-covering! end
net_from_port (_cap_input_node_for_return_of_add₁)-covering! end
net_from_port (add₃)-return
(add₃)-target!value-(add1₃)
(add₃)-addend value-(add1₂)
Expand Down

0 comments on commit 247cd65

Please sign in to comment.