[rtl] fix reduce.

chipsalliance · Nov 12, 2024 · ae33cd9 · ae33cd9
1 parent b1eaac3
commit ae33cd9
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/t1/src/mask/MaskReduce.scala b/t1/src/mask/MaskReduce.scala
@@ -149,7 +149,9 @@ class MaskReduce(parameter: T1Parameter) extends Module {
     cutUInt(reqReg.source2, parameter.datapathWidth)
   )
   val sourceValidCalculate: UInt =
-    reqReg.fpSourceValid.map(fv => Mux(floatType, fv & reqReg.sourceValid, fv)).getOrElse(reqReg.sourceValid)
+    reqReg.fpSourceValid.map(fv =>
+      Mux(floatType, fv & reqReg.sourceValid, reqReg.sourceValid)
+    ).getOrElse(reqReg.sourceValid)
   sourceValid := Mux1H(
     UIntToOH(crossFoldCount),
     sourceValidCalculate.asBools