[rtl] fix vmv.

chipsalliance · Nov 13, 2024 · 0ecb3be · 0ecb3be
1 parent b9034d7
commit 0ecb3be
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Showing 2 changed files with 19 additions and 17 deletions.
diff --git a/t1/src/mask/MaskCompress.scala b/t1/src/mask/MaskCompress.scala
@@ -196,10 +196,10 @@ class MaskCompress(parameter: T1Parameter) extends Module {
   )
 
   // todo
-  out.compressValid := compressTailValid || (compressDeqValid && in.fire)
+  out.compressValid := (compressTailValid || (compressDeqValid && in.fire)) && !mvRd
   out.groupCounter  := Mux(compress, compressWriteGroupCount, in.bits.groupCounter)
 
-  when(newInstruction) {
+  when(newInstruction && ffoType) {
     ffoIndex := -1.S(parameter.datapathWidth.W).asUInt
     ffoValid := false.B
   }

diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -205,11 +205,12 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val gatherGrowth:      UInt = RegEnable(reallyGrowth, 0.U, gatherRequestFire)
 
   val instReg:     MaskUnitInstReq = RegEnable(instReq.bits, 0.U.asTypeOf(instReq.bits), instReq.valid)
+  val enqMvRD:     Bool = instReq.bits.decodeResult(Decoder.topUop) === BitPat("b01011")
   val instVlValid: Bool            =
-    RegEnable(instReq.bits.vl.orR && instReq.valid, false.B, instReq.valid || lastReport.orR)
+    RegEnable((instReq.bits.vl.orR  || enqMvRD) && instReq.valid, false.B, instReq.valid || lastReport.orR)
   // viota mask read vs2. Also pretending to be reading vs1
   val viotaReq:    Bool            = instReq.bits.decodeResult(Decoder.topUop) === "b01000".U
-  when(instReq.valid && viotaReq || gatherRequestFire) {
+  when(instReq.valid && (viotaReq || enqMvRD) || gatherRequestFire) {
     instReg.vs1              := instReq.bits.vs2
     instReg.instructionIndex := instReq.bits.instructionIndex
   }
@@ -243,7 +244,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val pop:                 Bool = instReg.decodeResult(Decoder.popCount)
 
   // Instructions for writing vd without source
-  val noSource: Bool = mvVd || viota
+  val noSource: Bool = mv || viota
 
   val allGroupExecute: Bool = maskDestinationType || unitType(2) || compress || ffo
   val useDefaultSew:   Bool = unitType(0)
@@ -618,7 +619,8 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val anyDataValid:       Bool = exeReqReg.zipWithIndex.map { case (d, i) => d.valid }.reduce(_ || _)
 
   // try to read vs1
-  val readVs1Valid: Bool = (unitType(2) || compress) && !readVS1Reg.requestSend || gatherSRead
+  val readVs1Valid: Bool =
+    (unitType(2) || compress || mvRd) && !readVS1Reg.requestSend || gatherSRead
   readVS1Req.vs := instReg.vs1
   when(compress) {
     val logLaneNumber = log2Ceil(parameter.laneNumber)
@@ -677,15 +679,14 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val readTypeRequestDeq: Bool =
     (anyReadFire && groupReadFinish) || (readIssueStageValid && readIssueStageState.needRead === 0.U)
 
-  val noSourceValid:       Bool = noSource && counterValid && instReg.vl.orR
-  val vs1DataValid:        Bool = readVS1Reg.dataValid || !(unitType(2) || compress)
+  val noSourceValid:       Bool = noSource && counterValid &&
+    (instReg.vl.orR || (mvRd && !readVS1Reg.sendToExecution))
+  val vs1DataValid:        Bool = readVS1Reg.dataValid || !(unitType(2) || compress || mvRd)
   val executeReady:        Bool = Wire(Bool())
-  // todo: remove, it will do nothing when vl=0
-  val sendInitData:        Bool = unitType(2) && !readVS1Reg.sendToExecution && instReg.vl === 0.U
   val executeDeqReady:     Bool = VecInit(maskedWrite.in.map(_.ready)).asUInt.andR
   val otherTypeRequestDeq: Bool =
-    Mux(noSource, noSourceValid, allDataValid || sendInitData) &&
-      vs1DataValid && instVlValid && executeDeqReady || mvRd
+    Mux(noSource, noSourceValid, allDataValid) &&
+      vs1DataValid && instVlValid && executeDeqReady
   val requestStageDeq:     Bool = Mux(readType, readTypeRequestDeq, otherTypeRequestDeq && executeReady)
   val readIssueStageEnq:   Bool =
     (allDataValid || slideAddressGen.indexDeq.valid) &&
@@ -845,7 +846,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
     val read               = readData(index)
     read.ready := isWaiteForThisData
     if (index == 0) {
-      read.ready := isWaiteForThisData || unitType(2) || compress || gatherWaiteRead
+      read.ready := isWaiteForThisData || unitType(2) || compress || gatherWaiteRead || mvRd
       when(read.fire) {
         readVS1Reg.data      := read.bits
         readVS1Reg.dataValid := true.B
@@ -899,7 +900,8 @@ class MaskUnit(parameter: T1Parameter) extends Module {
     (selectVS1, willChangeVS1Index)
   }
 
-  val source1Data:   UInt = Mux1H(sew1H, vs1Split.map(_._1))
+  val compressSource1: UInt = Mux1H(sew1H, vs1Split.map(_._1))
+  val source1Select: UInt = Mux(mv, readVS1Reg.data, compressSource1)
   val source1Change: Bool = Mux1H(sew1H, vs1Split.map(_._2))
   when(source1Change && compressUnit.in.fire) {
     readVS1Reg.dataValid   := false.B
@@ -914,7 +916,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   compressUnit.in.bits.eew            := instReg.sew
   compressUnit.in.bits.uop            := instReg.decodeResult(Decoder.topUop)
   compressUnit.in.bits.readFromScalar := instReg.readFromScala
-  compressUnit.in.bits.source1        := source1Data
+  compressUnit.in.bits.source1        := source1Select
   compressUnit.in.bits.mask           := executeElementMask
   compressUnit.in.bits.source2        := source2
   compressUnit.in.bits.groupCounter   := requestCounter
@@ -943,7 +945,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
     sink := VecInit(exeReqReg.map(_.bits.fpReduceValid.get)).asUInt
   }
 
-  when(reduceUnit.in.fire) {
+  when(reduceUnit.in.fire || compressUnit.in.fire) {
     readVS1Reg.sendToExecution := true.B
   }
 
@@ -1090,7 +1092,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
     waiteStageDeqFire && waiteReadDataPipeReg.last,
     waiteLastRequest && maskedWrite.stageClear && executeStageInvalid
   )
-  val alwaysNeedExecute: Bool = WireInit(false.B) // todo: mv?
+  val alwaysNeedExecute: Bool = enqMvRD
   val invalidEnq:        Bool = instReq.fire && !instReq.bits.vl && !alwaysNeedExecute
   when(executeStageClean || invalidEnq) {
     waitQueueClear := true.B