[rtl] ix gather read.

chipsalliance · Nov 15, 2024 · 0237c9b · 0237c9b
1 parent a80387b
commit 0237c9b
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -202,7 +202,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
     gatherIndex(instReq.bits.readFromScala, instReq.bits.vlmul, instReq.bits.sew)
   val idle :: sRead :: wRead :: sResponse :: Nil = Enum(4)
   val gatherReadState:   UInt = RegInit(idle)
-  val gatherRequestFire: Bool = gatherReadState === idle && gatherRead
+  val gatherRequestFire: Bool = Wire(Bool())
   val gatherSRead:       Bool = gatherReadState === sRead
   val gatherWaiteRead:   Bool = gatherReadState === wRead
   val gatherResponse:    Bool = gatherReadState === sResponse
@@ -215,6 +215,7 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val enqMvRD:     Bool            = instReq.bits.decodeResult(Decoder.topUop) === BitPat("b01011")
   val instVlValid: Bool            =
     RegEnable((instReq.bits.vl.orR || enqMvRD) && instReq.valid, false.B, instReq.valid || lastReport.orR)
+  gatherRequestFire := gatherReadState === idle && gatherRead && !instVlValid
   // viota mask read vs2. Also pretending to be reading vs1
   val viotaReq:    Bool            = instReq.bits.decodeResult(Decoder.topUop) === "b01000".U
   when(instReq.valid && (viotaReq || enqMvRD) || gatherRequestFire) {