Merge pull request #44 from SyedHassanUlHaq/main

[GSOC] integrated support for Zvbc and Zvkg instructions

Makefile

@@ -55,7 +55,7 @@ CONFIGS = configs/
 
 SPIKE = spike
 PATCHER_SPIKE = build/pspike
-MARCH = rv${XLEN}gcv_zvbb
+MARCH = rv${XLEN}gcv_zvbb_zvbc_zvkg
 MABI = lp64d
 
 ifeq ($(XLEN), 32)

Makefrag

@@ -215,6 +215,12 @@ tests = \
   vasubu_vx-9 \
   vbrev8_v-0 \
   vbrev_v-0 \
+  vclmul_vv-0 \
+  vclmul_vx-0 \
+  vclmul_vx-1 \
+  vclmulh_vv-0 \
+  vclmulh_vx-0 \
+  vclmulh_vx-1 \
   vclz_v-0 \
   vcompress_vm-0 \
   vcpop_m-0 \
@@ -409,6 +415,7 @@ tests = \
   vfwsub_wf-0 \
   vfwsub_wf-1 \
   vfwsub_wv-0 \
+  vghsh_vv-0 \
   vid_v-0 \
   vid_v-1 \
   viota_m-0 \

configs/vclmul.vv.toml

@@ -0,0 +1,22 @@
+name = "vclmul.vv"
+format = "vd,vs2,vs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]

configs/vclmul.vx.toml

@@ -0,0 +1,22 @@
+name = "vclmul.vx"
+format = "vd,vs2,rs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]
+

configs/vclmulh.vv.toml

@@ -0,0 +1,21 @@
+name = "vclmulh.vv"
+format = "vd,vs2,vs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]

configs/vclmulh.vx.toml

@@ -0,0 +1,21 @@
+name = "vclmulh.vx"
+format = "vd,vs2,rs1,vm"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+sew64 = [
+    ["0xffffffffffff8000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0x0000000000000000"],
+    ["0xffffffff80000000", "0xffffffffffff8000"],
+    ["0x0000000000007fff", "0x0000000000000000"],
+    ["0x000000007fffffff", "0x0000000000007fff"],
+    ["0xffffffff80000000", "0x0000000000007fff"],
+    ["0x000000007fffffff", "0xffffffffffff8000"],
+    ["0xffffffffffffffff", "0x0000000000000001"],
+    ["0xffffffffffffffff", "0x0000000000000000"],
+    ["0xffffffffffffffff", "0xffffffffffffffff"]
+]

configs/vghsh.vv.toml

@@ -0,0 +1,19 @@
+name = "vghsh.vv"
+format = "vd,vs2,vs1"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+
+sew32 = [
+    [0xfffffff8, 0x00000000],
+    [0xffffff80, 0xfffffff8],
+    [0x00007fff, 0x00000000],
+    [0x00007fff, 0x000007ff],
+    [0x00007fff, 0x00000001],
+    [0xffffffff, 0x00000000],
+    [0xffffffff, 0xffffffff]
+]

configs/vgmul.vv.toml

@@ -0,0 +1,19 @@
+name = "vgmul.vv"
+format = "vd,vs2"
+
+[tests]
+base = [
+    [0x0, 0x0],
+    [0x1, 0x2],
+    [0x3, 0xf]
+]
+
+sew32 = [
+    [0xfffffff8, 0x00000000],
+    [0xffffff80, 0xfffffff8],
+    [0x00007fff, 0x00000000],
+    [0x00007fff, 0x000007ff],
+    [0x00007fff, 0x00000001],
+    [0xffffffff, 0x00000000],
+    [0xffffffff, 0xffffffff]
+]

generator/insn_util.go

@@ -179,4 +179,4 @@ func getVRegs(lmul1 LMUL, v0 bool, seed string) (int, int, int) {
 	})
 
 	return availableOptions[0], availableOptions[1], availableOptions[2]
-}
+}

generator/insn_vdvs2.go

@@ -9,39 +9,54 @@ import (
 )
 
 func (i *Insn) genCodeVdVs2(pos int) []string {
-	s := regexp.MustCompile(`vmv(\d)r.v`)
-	nr, err := strconv.Atoi(s.FindStringSubmatch(i.Name)[1])
-	if err != nil {
-		log.Fatal("unreachable")
+	zvkg_insn := strings.HasPrefix(i.Name, "vg")
+	sews := iff(zvkg_insn, []SEW{32}, allSEWs)
+
+	var nr int
+	var err error
+
+	if match := regexp.MustCompile(`vmv(\d+)r.v`).FindStringSubmatch(i.Name); len(match) > 1 {
+		nr, err = strconv.Atoi(match[1])
+		if err != nil {
+			log.Fatalf("Error parsing register number: %v", err)
+		}
 	}
 
-	combinations := i.combinations([]LMUL{LMUL(nr)}, allSEWs, []bool{false}, i.vxrms())
+	combinations := i.combinations([]LMUL{LMUL(nr)}, sews, []bool{false}, i.vxrms())
 	res := make([]string, 0, len(combinations))
 
 	for _, c := range combinations[pos:] {
+		if zvkg_insn && c.Vl % 4 != 0 {
+			c.Vl = (c.Vl + 3) / 4 * 4 
+		}
+
 		builder := strings.Builder{}
 		builder.WriteString(c.initialize())
+
+		var vd, vs2 int
+		if (zvkg_insn){
+			vd = int(c.LMUL1)
+			vs2 = 3 * int(c.LMUL1)
+		}else{
+			vd, vs2, _ = getVRegs(c.LMUL, true, i.Name)
+		}
 
-		vd, vs2, _ := getVRegs(c.LMUL, true, i.Name)
 		builder.WriteString(i.gWriteRandomData(c.LMUL * 2))
-
 		builder.WriteString(i.gLoadDataIntoRegisterGroup(vd, c.LMUL, c.SEW))
 		builder.WriteString(fmt.Sprintf("li t1, %d\n", int(c.LMUL)*i.vlenb()))
 		builder.WriteString(fmt.Sprintf("add a0, a0, t1\n"))
 		builder.WriteString(i.gLoadDataIntoRegisterGroup(vs2, c.LMUL, c.SEW))
 
 		builder.WriteString("# -------------- TEST BEGIN --------------\n")
 		builder.WriteString(i.gVsetvli(c.Vl, c.SEW, c.LMUL))
-		builder.WriteString(fmt.Sprintf("%s v%d, v%d\n",
-			i.Name, vd, vs2))
+		builder.WriteString(fmt.Sprintf("%s v%d, v%d\n", i.Name, vd, vs2))
 		builder.WriteString("# -------------- TEST END   --------------\n")
 
 		builder.WriteString(i.gResultDataAddr())
 		builder.WriteString(i.gStoreRegisterGroupIntoResultData(vd, c.LMUL, c.SEW))
 		builder.WriteString(i.gMagicInsn(vd, c.LMUL))
 
 		res = append(res, builder.String())
-
 	}
 
 	return res

generator/insn_vdvs2rs1vm.go

@@ -9,12 +9,14 @@ import (
 func (i *Insn) genCodeVdVs2Rs1Vm(pos int) []string {
 	vdWidening := strings.HasPrefix(i.Name, "vw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wx")
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")
 	vdSize := iff(vdWidening, 2, 1)
 	vs2Size := iff(vs2Widening, 2, 1)
 
 	sews := iff(vdWidening || vs2Widening, allSEWs[:len(allSEWs)-1], allSEWs)
+	sews = iff(sew64Only, []SEW{64}, sews)
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, allLMULs),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),

generator/insn_vdvs2vs1.go

@@ -6,9 +6,19 @@ import (
 )
 
 func (i *Insn) genCodeVdVs2Vs1(pos int) []string {
-	combinations := i.combinations(allLMULs, allSEWs, []bool{false}, i.vxrms())
+	zvkg_insn := strings.HasPrefix(i.Name, "vg")
+	sews := iff(zvkg_insn, []SEW{32}, allSEWs)
+	combinations := i.combinations(
+		allLMULs,
+		sews,
+		[]bool{false},
+		i.vxrms(),
+	)
 	res := make([]string, 0, len(combinations))
 	for _, c := range combinations[pos:] {
+		if zvkg_insn && c.Vl % 4 != 0 {
+			c.Vl = (c.Vl + 3) / 4 * 4 
+		}
 		builder := strings.Builder{}
 		builder.WriteString(c.initialize())
 

generator/insn_vdvs2vs1vm.go

@@ -8,15 +8,17 @@ import (
 
 func (i *Insn) genCodeVdVs2Vs1Vm(pos int) []string {
 	float := strings.HasPrefix(i.Name, "vf") || strings.HasPrefix(i.Name, "vmf")
+	sew64Only := strings.HasPrefix(i.Name, "vclmul")
 	vdWidening := strings.HasPrefix(i.Name, "vw") || strings.HasPrefix(i.Name, "vfw")
 	vs2Widening := strings.HasSuffix(i.Name, ".wv")
 	vdSize := iff(vdWidening, 2, 1)
 	vs2Size := iff(vs2Widening, 2, 1)
 
 	sews := iff(float, floatSEWs, allSEWs)
 	sews = iff(vdWidening || vs2Widening, sews[:len(sews)-1], sews)
+	sews = iff(sew64Only, []SEW{64}, sews)
 	combinations := i.combinations(
-		iff(vdWidening || vs2Widening, wideningMULs, allLMULs),
+		iff(vdWidening || vs2Widening, wideningMULs, iff(sew64Only, []LMUL{1, 2, 4, 8}, allLMULs)),
 		sews,
 		[]bool{false, true},
 		i.vxrms(),

main.go

@@ -100,6 +100,7 @@ func main() {
 			}
 			insn, err := generator.ReadInsnFromToml(contents, option)
 			fatalIf(err)
+
 			if insn.Name != strings.Replace(file.Name(), ".toml", "", -1) {
 				fatalIf(errors.New("filename and instruction name unmatched"))
 			}
@@ -130,4 +131,4 @@ func writeTo(path string, name string, contents string) {
 	fatalIf(err)
 	err = os.WriteFile(filepath.Join(path, name), []byte(contents), 0644)
 	fatalIf(err)
-}
+}