[GSOC] added allowed LMUL for Zvkg

chipsalliance · Aug 20, 2024 · b9c9f6d · b9c9f6d
1 parent b38eb22
commit b9c9f6d
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Showing 4 changed files with 27 additions and 16 deletions.
diff --git a/generator/insn_util.go b/generator/insn_util.go
@@ -81,12 +81,23 @@ func (l LMUL) String() string {
 	return fmt.Sprintf("m%d", int(l))
 }
 
-type VLEN int
-
-func (v VLEN) Zvkg_validVLEN() bool{
-	return 128 <= v && v <= 4096 && v&(v-1) == 0
+func ZvkgAllowedLMULs(vlen VLEN) []LMUL {
+	switch vlen {
+	case 64:
+		return []LMUL{2, 4, 8}
+	case 128:
+		return []LMUL{1, 2, 4, 8}
+	case 256:
+		return []LMUL{LMUL(1) / 2, 1, 2, 4, 8}
+	case 512:
+		return []LMUL{LMUL(1) / 4, LMUL(1) / 2, 1, 2, 4, 8}
+	default:
+		return allLMULs
+	}
 }
 
+type VLEN int
+
 func (v VLEN) Valid() bool {
 	return 64 <= v && v <= 4096 && v&(v-1) == 0
 }

diff --git a/generator/insn_vdvs2.go b/generator/insn_vdvs2.go
@@ -22,8 +22,9 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 		}
 	}
 
+	vlen := i.Option.VLEN
 
-	combinations := i.combinations(iff(zvkg_insn, []LMUL{1, 2, 4, 8}, []LMUL{LMUL(nr)}), iff(zvkg_insn, sew32_only, allSEWs), []bool{false}, i.vxrms())
+	combinations := i.combinations(iff(zvkg_insn, ZvkgAllowedLMULs(vlen), []LMUL{LMUL(nr)}), iff(zvkg_insn, sew32_only, allSEWs), []bool{false}, i.vxrms())
 	res := make([]string, 0, len(combinations))
 
 	for _, c := range combinations[pos:] {
@@ -33,10 +34,16 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 
 		builder := strings.Builder{}
 		builder.WriteString(c.initialize())
+
+		var vd, vs2 int
+		if (zvkg_insn){
+			vd = int(c.LMUL1)
+			vs2 = 3 * int(c.LMUL1)
+		}else{
+			vd, vs2, _ = getVRegs(c.LMUL, true, i.Name)
+		}
 
-		vd, vs2, _ := getVRegs(c.LMUL, true, i.Name)
 		builder.WriteString(i.gWriteRandomData(c.LMUL * 2))
-
 		builder.WriteString(i.gLoadDataIntoRegisterGroup(vd, c.LMUL, c.SEW))
 		builder.WriteString(fmt.Sprintf("li t1, %d\n", int(c.LMUL)*i.vlenb()))
 		builder.WriteString(fmt.Sprintf("add a0, a0, t1\n"))

diff --git a/generator/insn_vdvs2vs1.go b/generator/insn_vdvs2vs1.go
@@ -8,8 +8,9 @@ import (
 func (i *Insn) genCodeVdVs2Vs1(pos int) []string {
 	zvkg_insn := strings.HasPrefix(i.Name, "vg")
 	sew32_only := iff(zvkg_insn, []SEW{32}, allSEWs)
+	vlen := i.Option.VLEN
 	combinations := i.combinations(
-		iff(zvkg_insn, []LMUL{1, 2, 4, 8}, allLMULs),
+		iff(zvkg_insn, ZvkgAllowedLMULs(vlen), allLMULs),
 		iff(zvkg_insn, sew32_only, allSEWs),
 		[]bool{false},
 		i.vxrms(),

diff --git a/main.go b/main.go
@@ -101,14 +101,6 @@ func main() {
 			insn, err := generator.ReadInsnFromToml(contents, option)
 			fatalIf(err)
 
-			if strings.HasPrefix(insn.Name, "vg") && !option.VLEN.Zvkg_validVLEN() {
-                lk.Lock()
-                fmt.Printf("\033[0;1;31mskipping:\033[0m %s, VLEN is not greater than or equal to 128\n", name)
-                lk.Unlock()
-                wg.Done()
-                return
-            }
-
 			if insn.Name != strings.Replace(file.Name(), ".toml", "", -1) {
 				fatalIf(errors.New("filename and instruction name unmatched"))
 			}