Update to latest spike

.github/workflows/build-and-test.yml

@@ -44,7 +44,7 @@ jobs:
         run: |
           git clone https://github.com/riscv-software-src/riscv-isa-sim.git
           cd riscv-isa-sim
-          git reset --hard 3a53c80ade3336b1d46c9db3a6c6be8311c32cc5
+          git reset --hard [email protected]:chipsalliance/riscv-vector-tests.git
           mkdir build
           cd build
           ../configure --prefix=${{ github.workspace }}/riscv

Makefile

@@ -4,7 +4,7 @@
 ##
 ##Usage: make all -j$(nproc) --environment-overrides [OPTIONS]
 ##
-##Example: to generate isa=rv32gcv varch=vlen:128,elen:32 mode=machine tests, use:
+##Example: to generate isa=rv32gcv_zvl128b_zve32f mode=machine tests, use:
 ## make all --environment-overrides VLEN=128 XLEN=32 MODE=machine -j$(nproc)
 ##
 ##Subcommands:
@@ -60,6 +60,9 @@ MABI = lp64d
 
 ifeq ($(XLEN), 32)
 MABI = ilp32f
+VARCH = zvl${VLEN}b_zve32f
+else
+VARCH = zvl${VLEN}b_zve64d
 endif
 
 RISCV_PREFIX = riscv64-unknown-elf-
@@ -127,7 +130,7 @@ patching-stage2: build-patcher-spike compile-stage1
 	$(MAKE) $(tests_patch)
 
 $(tests_patch):
-	LD_LIBRARY_PATH=$(SPIKE_INSTALL)/lib ${PATCHER_SPIKE} --isa=${MARCH} --varch=vlen:${VLEN},elen:${XLEN} $(PK) ${OUTPUT_STAGE1_BIN}$(shell basename $@ .patch) > ${OUTPUT_STAGE2_PATCH}$@
+	LD_LIBRARY_PATH=$(SPIKE_INSTALL)/lib ${PATCHER_SPIKE} --isa=${MARCH}_${VARCH} $(PK) ${OUTPUT_STAGE1_BIN}$(shell basename $@ .patch) > ${OUTPUT_STAGE2_PATCH}$@
 
 generate-stage2: patching-stage2
 	build/merger -stage1output ${OUTPUT_STAGE1} -stage2output ${OUTPUT_STAGE2} -stage2patch ${OUTPUT_STAGE2_PATCH}
@@ -140,7 +143,7 @@ tests_stage2 = $(addsuffix .stage2, $(tests))
 
 $(tests_stage2):
 	$(RISCV_GCC) -march=${MARCH} -mabi=${MABI} $(RISCV_GCC_OPTS) $(STAGE2_GCC_OPTS) -I$(ENV) -Imacros/general -T$(ENV)/link.ld $(ENV_CSRCS) ${OUTPUT_STAGE2}$(shell basename $@ .stage2).S -o ${OUTPUT_STAGE2_BIN}$(shell basename $@ .stage2)
-	${SPIKE} --isa=${MARCH} --varch=vlen:${VLEN},elen:${XLEN} $(PK) ${OUTPUT_STAGE2_BIN}$(shell basename $@ .stage2)
+	${SPIKE} --isa=${MARCH}_${VARCH} $(PK) ${OUTPUT_STAGE2_BIN}$(shell basename $@ .stage2)
 
 
 clean-out:

pspike/pspike.cc

@@ -62,7 +62,6 @@ int main(int argc, char** argv) {
   cfg_t cfg;
   option_parser_t parser;
   parser.option(0, "isa", 1, [&](const char* s){cfg.isa = s;});
-  parser.option(0, "varch", 1, [&](const char* s){cfg.varch = s;});
   cfg.mem_layout = mem_layout;
 
   auto argv1 = parser.parse(argv);
@@ -80,10 +79,10 @@ int main(int argc, char** argv) {
     .support_impebreak = true
   };
   std::vector<std::pair<reg_t, abstract_mem_t*>> mems = make_mems(cfg.mem_layout);
-  std::vector<device_factory_t*> plugin_devices;
+  std::vector<device_factory_sargs_t> plugin_device_factories;
   sim_t sim(&cfg, false,
             mems,
-            plugin_devices,
+            plugin_device_factories,
             htif_args,
             dm_config,
             nullptr,