Change macro for dut w/o F support

- add RVTEST_RV{32,64}UVX - add RVTEST_ZVE32X_ENABLE Signed-off-by: Avimitin <[email protected]>
chipsalliance · Dec 21, 2024 · 3097a0f · 3097a0f
1 parent 52cd473
commit 3097a0f
Showing 1 changed file with 15 additions and 0 deletions.
diff --git a/env/ps/riscv_test.h b/env/ps/riscv_test.h
@@ -24,6 +24,11 @@
   RVTEST_VECTOR_ENABLE;                                                 \
   .endm
 
+#define RVTEST_RV64UVX                                                  \
+  .macro init;                                                          \
+  RVTEST_ZVE32X_ENABLE;                                                 \
+  .endm
+
 #define RVTEST_RV32U                                                    \
   .macro init;                                                          \
   .endm
@@ -38,6 +43,11 @@
   RVTEST_VECTOR_ENABLE;                                                 \
   .endm
 
+#define RVTEST_RV32UVX                                                  \
+  .macro init;                                                          \
+  RVTEST_ZVE32X_ENABLE;                                                 \
+  .endm
+
 #define RVTEST_RV64M                                                    \
   .macro init;                                                          \
   RVTEST_ENABLE_MACHINE;                                                \
@@ -112,6 +122,11 @@
   csrwi fcsr, 0;                                                        \
   csrwi vcsr, 0;
 
+#define RVTEST_ZVE32X_ENABLE                                            \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1));                              \
+  csrs mstatus, a0;                                                     \
+  csrwi vcsr, 0;
+
 #define RISCV_MULTICORE_DISABLE                                         \
   csrr a0, mhartid;                                                     \
   1: bnez a0, 1b