[GSOC] modified generator to support zvksed

chipsalliance · Aug 21, 2024 · 2c1771d · 2c1771d
1 parent 7bf31b8
commit 2c1771d
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Showing 4 changed files with 8 additions and 6 deletions.
diff --git a/Makefile b/Makefile
@@ -55,7 +55,7 @@ CONFIGS = configs/
 
 SPIKE = spike
 PATCHER_SPIKE = build/pspike
-MARCH = rv${XLEN}gcv_zvbb_zvbc_zvkg_zvkned
+MARCH = rv${XLEN}gcv_zvbb_zvbc_zvkg_zvkned_zvksed
 MABI = lp64d
 
 ifeq ($(XLEN), 32)

diff --git a/Makefrag b/Makefrag
@@ -1327,6 +1327,8 @@ tests = \
   vsll_vx-5 \
   vsll_vx-6 \
   vsll_vx-7 \
+  vsm4k_vi-0 \
+  vsm4k_vi-1 \
   vsm_v-0 \
   vsmul_vv-0 \
   vsmul_vv-1 \

diff --git a/generator/insn_vdvs2.go b/generator/insn_vdvs2.go
@@ -9,8 +9,8 @@ import (
 )
 
 func (i *Insn) genCodeVdVs2(pos int) []string {
-	zvkg_insn := strings.HasPrefix(i.Name, "vg")
-	sews := iff(zvkg_insn, []SEW{32}, allSEWs)
+	sew32Only_insn := strings.HasPrefix(i.Name, "vg") || strings.HasPrefix(i.Name, "vsm4")
+	sews := iff(sew32Only_insn, []SEW{32}, allSEWs)
 
 	var nr int
 	var err error
@@ -26,15 +26,15 @@ func (i *Insn) genCodeVdVs2(pos int) []string {
 	res := make([]string, 0, len(combinations))
 
 	for _, c := range combinations[pos:] {
-		if zvkg_insn && c.Vl % 4 != 0 {
+		if sew32Only_insn && c.Vl % 4 != 0 {
 			c.Vl = (c.Vl + 3) / 4 * 4 
 		}
 
 		builder := strings.Builder{}
 		builder.WriteString(c.initialize())
 
 		var vd, vs2 int
-		if (zvkg_insn){
+		if (sew32Only_insn){
 			vd = int(c.LMUL1)
 			vs2 = 3 * int(c.LMUL1)
 		}else{

diff --git a/generator/insn_vdvs2uimm.go b/generator/insn_vdvs2uimm.go
@@ -7,7 +7,7 @@ import (
 )
 
 func (i *Insn) genCodeVdVs2Uimm(pos int) []string {
-	sew32Only_insn := strings.HasPrefix(i.Name, "vaes")
+	sew32Only_insn := strings.HasPrefix(i.Name, "vaes") || strings.HasPrefix(i.Name, "vsm4")
 	sews := iff(sew32Only_insn, []SEW{32}, allSEWs)
 	vs2Size := 1
 	vdSize := 1