Fix lmul for vsext and vzext

chipsalliance · Feb 5, 2024 · 1dd70bf · 1dd70bf
1 parent d9cef06
commit 1dd70bf
Showing 1 changed file with 12 additions and 8 deletions.
diff --git a/generator/insn_vdvs2vmp3.go b/generator/insn_vdvs2vmp3.go
@@ -30,22 +30,26 @@ func (i *Insn) genCodeVdVs2VmP3(pos int) []string {
 		builder.WriteString(i.gLoadDataIntoRegisterGroup(0, c.LMUL1, c.SEW))
 
 		vs2EEW := c.SEW / SEW(f)
-		if vs2EEW > SEW(i.Option.XLEN) {
+		if vs2EEW < 8 {
 			res = append(res, "")
 			continue
 		}
 
-		vdEMUL := c.LMUL * LMUL(f)
+		vdEMUL := c.LMUL / LMUL(f)
+		if vdEMUL < 1/8 {
+			res = append(res, "")
+			continue
+		}
 		vdEMUL1 := LMUL(math.Max(float64(vdEMUL), 1))
 
-		vd := int(vdEMUL1)
-		vs2 := 2 * int(vdEMUL1)
+		vd := int(c.LMUL1)
+		vs2 := 2 * int(c.LMUL1)
 
 		builder.WriteString(i.gWriteRandomData(c.LMUL1))
-		builder.WriteString(i.gLoadDataIntoRegisterGroup(vd, vdEMUL1, c.SEW))
+		builder.WriteString(i.gLoadDataIntoRegisterGroup(vd, c.LMUL1, c.SEW))
 
-		builder.WriteString(i.gWriteIntegerTestData(c.LMUL1, vs2EEW, 0))
-		builder.WriteString(i.gLoadDataIntoRegisterGroup(vs2, c.LMUL1, vs2EEW))
+		builder.WriteString(i.gWriteIntegerTestData(vdEMUL1, vs2EEW, 0))
+		builder.WriteString(i.gLoadDataIntoRegisterGroup(vs2, vdEMUL1, vs2EEW))
 
 		builder.WriteString("# -------------- TEST BEGIN --------------\n")
 		builder.WriteString(i.gVsetvli(c.Vl, c.SEW, c.LMUL))
@@ -54,7 +58,7 @@ func (i *Insn) genCodeVdVs2VmP3(pos int) []string {
 		builder.WriteString("# -------------- TEST END   --------------\n")
 
 		builder.WriteString(i.gResultDataAddr())
-		builder.WriteString(i.gStoreRegisterGroupIntoResultData(vd, vdEMUL1, c.SEW))
+		builder.WriteString(i.gStoreRegisterGroupIntoResultData(vd, c.LMUL1, c.SEW))
 		builder.WriteString(i.gMagicInsn(vd))
 
 		res = append(res, builder.String())