Fix strided segment store (for #59)

chipsalliance · Dec 20, 2024 · 1d79486 · 1d79486
1 parent 5bd2b3d
commit 1d79486
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Showing 5 changed files with 21 additions and 45 deletions.
diff --git a/Makefrag b/Makefrag
@@ -1522,6 +1522,7 @@ tests = \
   vsll_vx-6 \
   vsll_vx-7 \
   vsm3c_vi-0 \
+  vsm3c_vi-1 \
   vsm3me_vv-0 \
   vsm4k_vi-0 \
   vsm4k_vi-1 \
@@ -1656,18 +1657,10 @@ tests = \
   vsrl_vx-7 \
   vsse16_v-0 \
   vsse16_v-1 \
-  vsse16_v-2 \
-  vsse16_v-3 \
   vsse32_v-0 \
-  vsse32_v-1 \
-  vsse32_v-2 \
   vsse64_v-0 \
-  vsse64_v-1 \
-  vsse64_v-2 \
   vsse8_v-0 \
   vsse8_v-1 \
-  vsse8_v-2 \
-  vsse8_v-3 \
   vsseg2e16_v-0 \
   vsseg2e32_v-0 \
   vsseg2e64_v-0 \
@@ -1834,42 +1827,31 @@ tests = \
   vssrl_vx-9 \
   vssseg2e16_v-0 \
   vssseg2e16_v-1 \
-  vssseg2e16_v-2 \
   vssseg2e32_v-0 \
   vssseg2e32_v-1 \
-  vssseg2e32_v-2 \
   vssseg2e64_v-0 \
-  vssseg2e64_v-1 \
   vssseg2e8_v-0 \
   vssseg2e8_v-1 \
-  vssseg2e8_v-2 \
-  vssseg2e8_v-3 \
   vssseg3e16_v-0 \
   vssseg3e16_v-1 \
-  vssseg3e16_v-2 \
   vssseg3e32_v-0 \
   vssseg3e32_v-1 \
   vssseg3e64_v-0 \
-  vssseg3e64_v-1 \
   vssseg3e8_v-0 \
   vssseg3e8_v-1 \
   vssseg3e8_v-2 \
-  vssseg3e8_v-3 \
   vssseg4e16_v-0 \
   vssseg4e16_v-1 \
   vssseg4e16_v-2 \
   vssseg4e32_v-0 \
   vssseg4e32_v-1 \
-  vssseg4e32_v-2 \
   vssseg4e64_v-0 \
   vssseg4e64_v-1 \
   vssseg4e8_v-0 \
   vssseg4e8_v-1 \
   vssseg4e8_v-2 \
-  vssseg4e8_v-3 \
   vssseg5e16_v-0 \
   vssseg5e16_v-1 \
-  vssseg5e16_v-2 \
   vssseg5e32_v-0 \
   vssseg5e32_v-1 \
   vssseg5e64_v-0 \
@@ -1899,13 +1881,16 @@ tests = \
   vssseg8e16_v-0 \
   vssseg8e16_v-1 \
   vssseg8e16_v-2 \
+  vssseg8e16_v-3 \
   vssseg8e32_v-0 \
   vssseg8e32_v-1 \
+  vssseg8e32_v-2 \
   vssseg8e64_v-0 \
   vssseg8e8_v-0 \
   vssseg8e8_v-1 \
   vssseg8e8_v-2 \
   vssseg8e8_v-3 \
+  vssseg8e8_v-4 \
   vssub_vv-0 \
   vssub_vv-1 \
   vssub_vv-2 \

diff --git a/generator/insn.go b/generator/insn.go
@@ -348,10 +348,12 @@ RVTEST_CODE_END
 }
 
 func (i *Insn) genData() string {
-	dataSize := i.vlenb() * (8 /* max LMUL */)
+	dataSize := i.vlenb() * 8 /* max LMUL */ * 8 /* max NFIELDS */
 	// Stride insns
 	if strings.HasPrefix(i.Name, "vlse") ||
-		strings.HasPrefix(i.Name, "vsse") {
+		strings.HasPrefix(i.Name, "vsse") ||
+		strings.HasPrefix(i.Name, "vlsse") ||
+		strings.HasPrefix(i.Name, "vssse") {
 		dataSize *= strides
 	} else if strings.HasPrefix(i.Name, "vw") ||
 		strings.HasPrefix(i.Name, "vfw") {

diff --git a/generator/insn_vdrs1mvs2vm.go b/generator/insn_vdrs1mvs2vm.go
@@ -36,8 +36,8 @@ func (i *Insn) genCodeVdRs1mVs2Vm(pos int) []string {
 			vd := int(c.LMUL1)
 
 			vs2 := 0
-			for k := vd+int(c.LMUL1)*nfields; true; k += 1 {
-				if k % int(emul) == 0 {
+			for k := vd + int(c.LMUL1)*nfields; true; k += 1 {
+				if k%int(emul) == 0 {
 					vs2 = k
 					break
 				}

diff --git a/generator/insn_vs3rs1mrs2vm.go b/generator/insn_vs3rs1mrs2vm.go
@@ -23,40 +23,29 @@ func (i *Insn) genCodeVs3Rs1mRs2Vm(pos int) []string {
 		builder.WriteString(i.gLoadDataIntoRegisterGroup(0, LMUL(1), SEW(32)))
 
 		vs3 := int(c.LMUL1)
-		for _, s := range []int{minStride, 0, 1, maxStride} {
-			stride := s * int(c.SEW) / 8
-
+		for _, s := range []int{1, maxStride} {
 			builder.WriteString(i.gWriteIntegerTestData(c.LMUL1*LMUL(nfields), c.SEW, 0))
 			for nf := 0; nf < nfields; nf++ {
 				builder.WriteString(i.gLoadDataIntoRegisterGroup(vs3+(nf*int(c.LMUL1)), c.LMUL1, c.SEW))
-				builder.WriteString(fmt.Sprintf("li a5, %d\n", stride*i.vlenb()*int(c.LMUL1)))
-				builder.WriteString("add a0, a0, a5\n")
 			}
 
 			builder.WriteString(i.gResultDataAddr())
-			builder.WriteString(fmt.Sprintf("li a5, %d\n", -minStride*i.vlenb()*int(c.LMUL1)))
-			builder.WriteString("add a0, a0, a5\n")
 
 			builder.WriteString("# -------------- TEST BEGIN --------------\n")
-			builder.WriteString(fmt.Sprintf("li s0, %d # stride\n", stride))
+			builder.WriteString(fmt.Sprintf("li s0, %d # stride\n", s*int(i.vlenb())*int(c.LMUL1)))
 			builder.WriteString(i.gVsetvli(c.Vl, c.SEW, c.LMUL))
 			builder.WriteString(fmt.Sprintf("%s v%d, (a0), s0%s\n", i.Name, vs3, v0t(c.Mask)))
 			builder.WriteString("# -------------- TEST END   --------------\n")
 
-			builder.WriteString(fmt.Sprintf("li a5, %d\n", minStride*i.vlenb()*int(c.LMUL1)))
-			builder.WriteString("add a0, a0, a5\n")
-
 			builder.WriteString("mv a4, a0\n")
-			for a := 0; a < strides; a++ {
-				builder.WriteString(i.gLoadDataIntoRegisterGroup(vs3, c.LMUL1, c.SEW))
-				builder.WriteString(i.gMagicInsn(vs3, c.LMUL1))
-				builder.WriteString(fmt.Sprintf("li a5, %d\n", i.vlenb()*int(c.LMUL1)))
-				builder.WriteString(fmt.Sprintf("add a4, a4, a5\n"))
-				builder.WriteString("mv a0, a4\n")
+			for nf := 0; nf < nfields; nf++ {
+				for a := 0; a < maxStride; a++ {
+					builder.WriteString(i.gLoadDataIntoRegisterGroup(vs3+(nf*int(c.LMUL1)), c.LMUL1, c.SEW))
+					builder.WriteString(i.gMagicInsn(vs3+(nf*int(c.LMUL1)), c.LMUL1))
+					builder.WriteString(fmt.Sprintf("li a5, %d\n", i.vlenb()*int(c.LMUL1)))
+					builder.WriteString(fmt.Sprintf("add a0, a4, a5\n"))
+				}
 			}
-
-			builder.WriteString(fmt.Sprintf("li a5, %d\n", -strides*i.vlenb()*int(c.LMUL1)))
-			builder.WriteString("add a0, a0, a5\n")
 		}
 
 		res = append(res, builder.String())

diff --git a/generator/insn_vs3rs1mvs2vm.go b/generator/insn_vs3rs1mvs2vm.go
@@ -37,8 +37,8 @@ func (i *Insn) genCodeVs3Rs1mVs2Vm(pos int) []string {
 			vs3 := int(c.LMUL1)
 
 			vs1 := 0
-			for k := vs3+int(c.LMUL1)*nfields; true; k += 1 {
-				if k % int(emul) == 0 {
+			for k := vs3 + int(c.LMUL1)*nfields; true; k += 1 {
+				if k%int(emul) == 0 {
 					vs1 = k
 					break
 				}