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@AWSwinefred AWSwinefred released this 14 Apr 14:49
· 207 commits to master since this release
v1.1.0
f18d802

Release 1.1.0 New Features Details

The following new features are included in this HDK release:

1. New Shell, with modified Shell/CL interface. Changes are covered in:

  • New Shell Stable: 0x032117d7
  • cl_ports.vh have the updated port list
  • Removed all the ifdef and ifndef from the cl_ports.vh
  • Added all the interfaces required for SDAccel platform support
  • AWS_Shell_Interface_Specification.md has been updated
  • Updated the xdc timing constrains under constraints to match the new interfaces (WIP)
  • Updated CL HELLO WORLD example to use the new cl_ports.vh
  • Updated clean_log.pl scripts (WIP)
  • DCP for the latest shell v032117d7. AWS Shell DCP is now stored in S3 and fetched/verified when hdk_setup.sh script is sourced.

2. New Integrated DMA. AWS Shell now includes DMA capabilities on behalf of the CL

  • The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4
  • DMA usage is covered in the new CL_DRAM_DMA example RTL verification/simulation and Software
  • A corresponding AWS Elastic DMA (EDMA) driver is provided.
  • EDMA Installation Readme provides installation and usage guidlines
  • The initial release supports a single queue in each direction
  • Renamed sh_cl_pcis to sh_cl_dma_pcis

3. CL User-defined interrupt events. The CL can now request sending MSI-X to the instance CPU

  • Added new req/ack interface on Shell/CL interface
  • Usage covered in new CL_DRAM_DMA example: RTL verification/simulation and software (WIP)
  • A corresponding AWS EDMA driver is provided under /sdk/linux_kernel_drivers/edma
  • EDMA Installation provides installation and usage guidlines
  • The initial release supports a single user-defined interrupt

4. Added a Mandatory Manifest.txt file submitted with each DCP via create-fpga-image API

  • File content defined in AFI Manifest
  • AFI_Manifest.txt is created automatically if the developer is using the aws_build_dcp_from_cl.sh script
  • PCI Vendor ID and Device ID are now part of the manifest and no longer needed in create-fpga-image
  • Shell Version is part of the manifest and no longer needed in create-fpga-image
  • All the examples and documentations for build include the description and dependency on the Manifest.txt

5. create-fpga-image -shell_version and --pci* arguments are obsolete

  • From this version the shell_version, pci_vendor_id, pci_device_id, pci_subsystem_id and pci_subsystem_vendor_id arguments are mandatory parameters in manifest.txt that should be submitted within the tar file

6. Decoupling Shell/CL interface clocking from the internal Shell Clock

  • All the Shell/CL interfaces running off the newly introduced clk_main_a0, and no longer required to be 250Mhz.
  • The default frequency using the HDK build flow for clk_main_a0 is 125Mhz as specified in recipe number A0. Allowing CL designs to have flexible frequency and not be constrained to 250Mhz only. All CL designs must include the recipe number in the manifest.txt file in order to generate an AFI.
  • All xdc scripts have been updated to clk_main_a0 and to reference a table with the possible clocks’ frequencies combinations
  • Obsolete the cl_clk interface
  • Updated CL_HELLO_WORLD and CL_DRAM_DMA examples to use the clk_main_a0

7. Additional User-defined Auxiliary Clocks

Additional tunable auxiliary clocks are generated by the Shell and fed to the CL. The clocks frequencies are set by choosing a clock recipe per group from a set of predefined frequencies combination in clock recipes table

  • Clock frequency selection is set during build time, and recorded in the manifest.txt (which should include the clock_recipe_a/b/c parameters)
  • Clock frequency programming in the FPGA slot itself occurs when the AFI is loaded. The list of supported frequencies is available here
  • See AWS_Shell_Interface_Specification for details on the clocking to the CL
  • See AFI Manifest for details on the AFI manifest data
  • xdc is automatically updated with the target frequency (WIP)

8. Additional PCIe BARs and update PCIe Physical Function mapping

** The AppPF now has 4 different PCIe BARs:**

  • BAR0 and BAR1 have been expanded to support 32-bit access for different memory ranges of the CL through separate AXI-L interfaces
  • BAR2 is used exclusively for the DMA inside the Shell and MSI-X interrupt tables
  • BAR4 expanded to 128GiB to cover all external DRAM memory space

** ManagementPF added additional PCIe BARs:**

** MgmtPF and AppPF are now represented as different PCIe devices in F1 instances:**

  • Each FPGA Slot will now occupy two PCIe buses, one for AppPF and one for MgmtPF
  • No change is required on the developer's side as long as the developer is using fpga-image-tools linux shell commands and/or fpgamgmt.lib C-APIs.

9. Expanded AppPF BAR4 space to 128GiB

10. Added wider access on the Shell to CL AXI4 512-bit bus (sh_cl_dma_pcis)

  • Wider access provides higher bandwidth DMA and host to FPGA access
  • Instance CPU can now burst full 64-byte write burst to AppPF PCIe BAR4 if mapped as Burstable (a.k.a WC: WriteCombine) (WIP)
  • pci_poke_burst() and pci_poke64() calls were added to fpga_pci library to take advantage of this
  • CL_DRAM_DMA and CL_HELLO_WORLD examples support for a wider access was added

11. Support larger than 32-bit access to PCIe space

  • Large inbound transaction going to AppPF PCIe BAR4 will be passed onward to the CL
  • Large inbound transactions going to the other BARs will be split by the Shell to multiple 32-bit accesses, and satisfy AXI-L protocol specification.

12. Enhanced AXI4 error handling and reporting

  • Additional error conditions detected on the CL to Shell Interface and reported through fpga-describe-image tool
  • See AWS Shell Interface Specification for more details
  • FPGA Management Tool metrics output covers the additional error handling details

13. Expanded AXI ID space throughout the design

  • The AXI buses between Shell and CL support an expanded number of AXI ID bits to allow for bits to be added by AXI fabrics See AWS Shell Interface Specification for more details

14. Shell to CL interface metrics.

  • New metrics for monitoring the Shell to CL are available from the AFI Management Tools.
  • See fpga mgmt tools readme for more details

15. Virtual LED/DIP Switches.

  • Added CL capability to present virtual LEDs and push virtual DIP switches indications to the CL, set and read by FPGA Management Tools and without involving CL logic, providing the developer an environment similar to developing on local boards with LED and DIP switches
  • See new commands in FPGA Image Tools for description of the new functionality
  • CL_HELLO_WORLD example includes some logic to set LED and adjust according to vDIP
  • See AWS Shell Interface Specification for more details

16. Virtual JTAG

  • The Shell has the capability for supporting CL integrated Xilinx debug cores like Virtual I/O (VIO) and Integrated Logic Analyzer (ILA) and includes support for local/remote debug by running XVC
  • Virtual_JTAG_XVC describes how to use Virtual JTAG from linux shell
  • cl_debug_bridge module was added to HDK common directory
  • Support for generating .ltx files after create-fpga-image was added. .ltx file is required when running interactive ILA/VIO debug (WIP)
  • Build tcl and xdc includes the required changes to enable Virtual JTAG
  • See CL_DRAM_DMA for examples on using Virtual JTAG and XVC for debug

17. Examples summary table

18. Updated CL_HELLO_WORLD Example

  • Matching the new Shell/CL interface
  • Add support for 32-bit peek/poke via ocl_ AXI-L bus
  • Adding Virtual JTAG support with Xilinx ILA and VIO debug cores (WIP)
  • Demonstrate the use of Virtual LED and Virtual DIPSwitch
  • Runtime software examples, leveraging fpga_pci and fpga_mgmt C-libraries
  • Updated PCIe Vendor ID and Device ID
  • See CL HELLO WORLD readme for more details

19. Added CL_DRAM_DMA Example

  • Mapping AppPF PCIe BAR4 to DRAM
  • Using DMA to access same DRAM
  • Using SystemVerilog Bus constructs to simplify the code
  • Demonstrate the use of User interrupts
  • Demonstrate the use of bar1_ AXI-L bus
  • Includes Runtime C-code application under CL_DRAM_DMA software (WIP)
  • See CL_DRAM_DMA README

20. Removed the CL_SIMPLE example

  • Moved the main functionality to CL_DRAM_DMA and removed the mapping AppPF PCIe BAR4 to DRAM

21. Software Programmer View document

22. Two C-libraries for FPGA PCIe access and for FPGA Management

  • The C-libraries are simplifying and adding more protections from developer’s mistakes when writing a runtime C-application
  • Fpga_mgmt.h cover the APIs for calling management functions
  • Fpga_pcie.h covers the API for access the various PCI memory spaces of the FPGA
  • CL_HELLO_WORLD and CL_DRAM_DMA examples updated to use these libraries.

23. VHDL support is added

  • Included Vivado encryption key file for VHDL
  • Added VHDL-specific line in encrypt.tcl reference files
  • Developer would need to add read_vhdl in create_dcp_from_cl.tcl

24. Additional FPGA Management Tools added

25. Upgrade to Vivado 2016.04-SDx Build

  • The FPGA Development AMI includes Vivado 2016.4-SDx
  • Older Vivado versions will not be supported

26. Embed the HDK version and Shell Version as part of git tree

27. Initial Release of SDAccel and OpenCL Support (NA)

  • Updated documentation in /sdk/SDAccel (NA)
  • OpenCL runtime HAL for supporting SDAccel and OpenCL ICD in /sdk/userspace (NA)
  • SDAccel build post-processing to register SDAccel xcl.bin as AFI. (NA)

28. Updates the /hdk/common Directory structures

  • To identify the shell_stable and shell_next directories for stable and work-in-progress shells respectively

29. Simplify create_dcp_from_cl.tcl and encrypt.tcl scripts

  • Reduced script complexity by consolidating CL design files list into one script.
  • The list of CL design source files would only need to be updated in encrypt.tcl script
  • Removed pr_verify stage from create_dcp_from_cl.tcl. PR (Partial Reconfiguration) verification is optional and customers

30. Simplify handling of unused Shell to CL interfaces

  • Developers can simply call `include "unused_BUS_NAME_template.inc" for every unused interface
  • List of potential files to include is available in $HDK_SHELL_DIR/design/interfaces/unused\*
  • cl_hello_world.sv and cl_dram_dma.sv provide examples (at the each of each file)

31. Support multiple Vivado versions

  • hdk_setup.sh compares between the list of Vivado versions supported by the HDK and the installed vivado versions
  • hdk_setup.sh would automatically choose the Vivado version from the available binaries in AWS FPGA Developer's AMI

32. Changes in DRAM controller setting to improve bandwidth utilization

  • Change address decoding to ROW_COL_INTLV mode
  • Enable auto precharge on COL A3
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