[QUESTIONS]projects:ad469x_iio: Added SPI DMA Support #85
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Added SPI DMA support for the AD4696 Signed-off-by: Janani Sunil <[email protected]>
| #if (INTERFACE_MODE == SPI_DMA) | ||
| /* If SPI_DMA is enabled, this pwm is also | ||
| * also used to trigger a spi tx dma transaction. | ||
| * */ |
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so cnv triggers tm8 in output compare mode with bytes per sample pulses (tim8_config)
but the pmw_desc is not used. (pmw_enable never called)
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| return ret; | ||
| } | ||
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| ret = no_os_pwm_disable(tx_trigger_desc); |
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where is tx_trigger_desc enabled?
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Tx trigger should not be manually enabled, as it is being operated in slave mode, where the CNV timer (timer 1 channel 3) acts as a master.
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| /* AD469x DMA Descriptor */ | ||
| struct no_os_dma_desc* ad469x_dma_desc; |
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where is this used?
| #if (INTERFACE_MODE == SPI_DMA) | ||
| /* PWM descriptor for controlling the CS pulse. | ||
| */ | ||
| struct no_os_pwm_desc *cs_desc; |
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where is this used?
| HAL_Init(); | ||
| SystemClock_Config(); | ||
| #if (INTERFACE_MODE == SPI_DMA) | ||
| /* If SPI_DMA mode is enabled, we don't need DMA initialization |
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you mean the opposite here... right?
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Yes, you are right, its a typo here.
| { | ||
| #if (INTERFACE_MODE == SPI_DMA) | ||
| TIM1->EGR = TIM_EGR_UG;// Generate update event | ||
| TIM1->CR2 = (TIM_CR2_MMS_COMPARE_PULSE * |
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multiplication for bit operations?
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| ret = no_os_dma_xfer_abort(sdesc->dma_desc, sdesc->rxdma_ch); | ||
| if (ret) { | ||
| return ret; |
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return int when return type for function is void.
| #endif | ||
| } | ||
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| void tim8_config(void) |
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these register mainpulations should be on drivers/platform/stm32/*?
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A few bitfield configurations aren't really handled in the platform driver layer. Also, since the DMA implementation is timing critical, we would want to keep it as in direct reg acces mode
| #define SAMPLING_RATE (62500) | ||
| #define CONV_TRIGGER_DUTY_CYCLE_NSEC(x) (x / 10) | ||
| #else | ||
| #define SAMPLING_RATE (500000) |
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was this tested with 1msps? or only up to 500ksps?
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This has been tested only upto 500ksps
| #define AD469x_DMA_NUM_CHANNELS 2 | ||
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| /* PWM configuration for 22.5MHz SPI clock */ | ||
| #define TX_TRIGGER_PERIOD 406 |
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so CS goes low in 300ns, stays low for 1700ns. (2000ns sample rate)
tx pulse at 406ns, and 812ns (2 bytes - 2 pulses per timer event)
is this correct?
Added SPI DMA support for the AD4696