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ad469x : coraz7s: Add axi_iic_ard for evb eeprom #1541

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merged 2 commits into from
Dec 10, 2024
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ad469x : coraz7s: Add axi_iic_ard for evb eeprom #1541

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4e040fc
docs: ad469x_evb: Update addr/irq with axi_iic_ard
gastmaier Dec 10, 2024
4ee7347
projects: ad469x: Use common axi_iic_ard
gastmaier Dec 10, 2024
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7 changes: 4 additions & 3 deletions docs/projects/ad469x_evb/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -159,9 +159,9 @@ I2C connections
- 0x4162_0000
- ---
* - PL**
- iic_main
- axi_ad469x_iic
- 0x44a4_0000
- iic_ard
- axi_iic_ard
- 0x4160_0000
- ---
* - PS***
- i2c1
Expand Down Expand Up @@ -261,6 +261,7 @@ Instance name HDL Linux Zynq Actual Zynq
================ === ========== ===========
axi_ad469x_dma 13 57 89
spi_ad469x 12 56 88
axi_iic_ard 11 55 87
================ === ========== ===========

================ === =============== ================
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9 changes: 0 additions & 9 deletions projects/ad469x_evb/coraz7s/system_bd.tcl
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Expand Up @@ -14,15 +14,6 @@ adi_project_files ad469x_evb_coraz7s [list \
# block design
source ../common/ad469x_bd.tcl

create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 ad469x_iic

ad_ip_instance axi_iic axi_ad469x_iic
ad_connect ad469x_iic axi_ad469x_iic/iic

ad_cpu_interconnect 0x44a40000 axi_ad469x_iic

ad_cpu_interrupt "ps-11" "mb-11" axi_ad469x_iic/iic2intc_irpt

#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
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3 changes: 0 additions & 3 deletions projects/ad469x_evb/coraz7s/system_constr.xdc
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Expand Up @@ -14,9 +14,6 @@ set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports a
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports ad469x_spi_cnv]; ## CK_IO06
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports ad469x_resetn]; ## CK_IO04

set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_scl]; ## CK_SCL
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_sda]; ## CK_SDA

# rename auto-generated clock for SPIEngine to spi_clk - 160MHz
# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
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8 changes: 4 additions & 4 deletions projects/ad469x_evb/coraz7s/system_top.v
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Expand Up @@ -64,8 +64,8 @@ module system_top #(
inout [1:0] btn,
inout [5:0] led,

inout iic_eeprom_scl,
inout iic_eeprom_sda,
inout iic_ard_scl,
inout iic_ard_sda,

// ad469x SPI configuration interface

Expand Down Expand Up @@ -155,8 +155,8 @@ module system_top #(
.ad469x_spi_busy (ad469x_busy_alt_gp0),
.ad469x_spi_cnv (ad469x_spi_cnv_s),
.gpio_cnv(gpio_o[34]),
.ad469x_iic_scl_io (iic_eeprom_scl),
.ad469x_iic_sda_io (iic_eeprom_sda),
.iic_ard_scl_io (iic_ard_scl),
.iic_ard_sda_io (iic_ard_sda),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
Expand Down
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