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M2k DAC buffer fixes #1180

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merged 2 commits into from
Dec 12, 2023
Merged

M2k DAC buffer fixes #1180

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74f82be
m2k: Remove dac last_sample_hold control
AndreiGrozav Sep 8, 2023
e2da33b
axi_dac_interpolate: Improve the ctrl logic
AndreiGrozav Sep 22, 2023
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9 changes: 0 additions & 9 deletions library/axi_ad9963/axi_ad9963.v
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Original file line number Diff line number Diff line change
Expand Up @@ -107,8 +107,6 @@ module axi_ad9963 #(
input dma_valid_q,
input dac_dunf,

input hold_last_sample,

// axi interface

input s_axi_aclk,
Expand Down Expand Up @@ -169,8 +167,6 @@ module axi_ad9963 #(
wire up_rack_tx_s;
wire up_adc_ce;
wire up_dac_ce;
wire valid_out_q_s;
wire valid_out_i_s;

// signal name changes

Expand Down Expand Up @@ -208,10 +204,7 @@ module axi_ad9963 #(
.adc_status (adc_status_s),
.up_adc_ce(up_adc_ce),
.dac_data (dac_data_s),
.out_valid_q (valid_out_q_s),
.out_valid_i (valid_out_i_s),
.up_dac_ce(up_dac_ce),
.tx_sample_hold (hold_last_sample),
.up_clk (up_clk),
.up_adc_dld (up_adc_dld_s),
.up_adc_dwdata (up_adc_dwdata_s),
Expand Down Expand Up @@ -288,12 +281,10 @@ module axi_ad9963 #(
.dac_valid_i (dac_valid_i),
.dac_data_i (dac_data_i),
.dma_valid_i (dma_valid_i),
.out_valid_i (valid_out_i_s),
.dac_enable_q (dac_enable_q),
.dac_valid_q (dac_valid_q),
.dac_data_q (dac_data_q),
.dma_valid_q (dma_valid_q),
.out_valid_q (valid_out_q_s),
.dac_dunf(dac_dunf),
.up_dac_ce(up_dac_ce),
.up_rstn (up_rstn),
Expand Down
30 changes: 4 additions & 26 deletions library/axi_ad9963/axi_ad9963_if.v
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Expand Up @@ -73,11 +73,8 @@ module axi_ad9963_if #(

// transmit data path interface

input out_valid_q,
input out_valid_i,
input [23:0] dac_data,
input up_dac_ce,
input tx_sample_hold,

// delay interface

Expand All @@ -93,16 +90,15 @@ module axi_ad9963_if #(
// internal registers

reg [11:0] rx_data_p = 0;
reg [11:0] tx_data_p = 'd0;
reg [11:0] tx_data_n = 'd0;
reg [23:0] constant_sample = 'd0;

// internal signals

wire [11:0] rx_data_p_s;
wire [11:0] rx_data_n_s;
wire rx_iq_p_s;
wire rx_iq_n_s;
wire [11:0] tx_data_p;
wire [11:0] tx_data_n;

wire div_clk;

Expand All @@ -119,26 +115,8 @@ module axi_ad9963_if #(
end
end

always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
tx_data_p <= 24'd0;
tx_data_n <= 24'd0;
constant_sample <= 24'd0;
end else begin
if(out_valid_i == 1'b1) begin
tx_data_p <= dac_data[11: 0];
constant_sample[11: 0] <= tx_sample_hold ? dac_data[11: 0] : 12'd0;
end else begin
tx_data_p <= constant_sample[11:0] ;
end
if(out_valid_q == 1'b1) begin
tx_data_n <= dac_data[23:12];
constant_sample[23:12] <= tx_sample_hold ? dac_data[23:12] : 12'd0;
end else begin
tx_data_n <= constant_sample[23:12];
end
end
end
assign tx_data_p = dac_data[11: 0];
assign tx_data_n = dac_data[23:12];

always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
Expand Down
4 changes: 0 additions & 4 deletions library/axi_ad9963/axi_ad9963_tx.v
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Original file line number Diff line number Diff line change
Expand Up @@ -68,12 +68,10 @@ module axi_ad9963_tx #(
output reg dac_valid_i,
input [15:0] dac_data_i,
input dma_valid_i,
output out_valid_i,
output dac_enable_q,
output reg dac_valid_q,
input [15:0] dac_data_q,
input dma_valid_q,
output out_valid_q,
input dac_dunf,

output up_dac_ce,
Expand Down Expand Up @@ -147,7 +145,6 @@ module axi_ad9963_tx #(
.dac_data_sync (dac_data_sync_s),
.dac_dds_format (dac_dds_format_s),
.dma_valid (dma_valid_i),
.out_data_valid (out_valid_i),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
Expand Down Expand Up @@ -181,7 +178,6 @@ module axi_ad9963_tx #(
.dac_data_sync (dac_data_sync_s),
.dac_dds_format (dac_dds_format_s),
.dma_valid (dma_valid_q),
.out_data_valid (out_valid_q),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
Expand Down
3 changes: 0 additions & 3 deletions library/axi_ad9963/axi_ad9963_tx_channel.v
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Expand Up @@ -58,7 +58,6 @@ module axi_ad9963_tx_channel #(
output reg [11:0] dac_data_out,
input [11:0] dac_data_in,
input dma_valid,
output out_data_valid,

// processor interface

Expand Down Expand Up @@ -113,8 +112,6 @@ module axi_ad9963_tx_channel #(
wire [15:0] dac_iqcor_coeff_1_s;
wire [15:0] dac_iqcor_coeff_2_s;

assign out_data_valid = dac_iqcor_valid_s;

// dac iq correction

always @(posedge dac_clk) begin
Expand Down
27 changes: 18 additions & 9 deletions library/axi_dac_interpolate/axi_dac_interpolate.v
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Expand Up @@ -58,7 +58,6 @@ module axi_dac_interpolate #(
output [15:0] dac_int_data_b,
output dac_valid_out_a,
output dac_valid_out_b,
output hold_last_sample,
output underflow,

input [ 1:0] trigger_i,
Expand Down Expand Up @@ -125,6 +124,7 @@ module axi_dac_interpolate #(
wire [ 2:0] filter_mask_b;

wire dma_transfer_suspend;
wire flush_dma_s;
wire start_sync_channels;

wire dac_correction_enable_a;
Expand Down Expand Up @@ -152,8 +152,10 @@ module axi_dac_interpolate #(
wire underflow_a;
wire underflow_b;

wire [ 1:0] lsample_hold_config;
wire sync_stop_channels;
wire stop_sync_channels;
wire [ 1:0] raw_transfer_en;
wire [15:0] dac_raw_ch_a_data;
wire [15:0] dac_raw_ch_b_data;

// signal name changes

Expand Down Expand Up @@ -206,9 +208,6 @@ module axi_dac_interpolate #(
low_level_trigger <= ~trigger_i_m3 & low_level;
end

assign hold_last_sample = lsample_hold_config[0];
assign sync_stop_channels = lsample_hold_config[1];

assign underflow = underflow_a | underflow_b;

axi_dac_interpolate_filter #(
Expand All @@ -220,7 +219,6 @@ module axi_dac_interpolate #(
.dac_data (dac_data_a),
.dac_valid (dac_valid_a),
.dac_valid_out (dac_valid_out_a),
.sync_stop_channels (sync_stop_channels),

.dac_enable (dac_enable_a),
.dac_int_data (dac_int_data_a),
Expand All @@ -231,6 +229,10 @@ module axi_dac_interpolate #(
.interpolation_ratio (interpolation_ratio_a),
.dma_transfer_suspend (dma_transfer_suspend),
.start_sync_channels (start_sync_channels),
.sync_stop_channels (stop_sync_channels),
.flush_dma_in (flush_dma_s),
.raw_transfer_en (raw_transfer_en[0]),
.dac_raw_ch_data (dac_raw_ch_a_data),
.trigger (trigger),
.trigger_active (trigger_active),
.en_start_trigger (en_start_trigger),
Expand All @@ -249,7 +251,6 @@ module axi_dac_interpolate #(
.dac_data (dac_data_b),
.dac_valid (dac_valid_b),
.dac_valid_out (dac_valid_out_b),
.sync_stop_channels (sync_stop_channels),
.underflow (underflow_b),

.dac_enable (dac_enable_b),
Expand All @@ -260,6 +261,10 @@ module axi_dac_interpolate #(
.interpolation_ratio (interpolation_ratio_b),
.dma_transfer_suspend (dma_transfer_suspend),
.start_sync_channels (start_sync_channels),
.sync_stop_channels (stop_sync_channels),
.flush_dma_in (flush_dma_s),
.raw_transfer_en (raw_transfer_en[1]),
.dac_raw_ch_data (dac_raw_ch_b_data),
.trigger (trigger),
.trigger_active (trigger_active),
.en_start_trigger (en_start_trigger),
Expand All @@ -279,13 +284,17 @@ module axi_dac_interpolate #(
.dac_filter_mask_b (filter_mask_b),

.dma_transfer_suspend (dma_transfer_suspend),
.flush_dma_out (flush_dma_s),
.raw_transfer_en (raw_transfer_en),
.dac_raw_ch_a_data (dac_raw_ch_a_data),
.dac_raw_ch_b_data (dac_raw_ch_b_data),
.start_sync_channels (start_sync_channels),
.dac_correction_enable_a(dac_correction_enable_a),
.dac_correction_enable_b(dac_correction_enable_b),
.dac_correction_coefficient_a(dac_correction_coefficient_a),
.dac_correction_coefficient_b(dac_correction_coefficient_b),
.trigger_config (trigger_config),
.lsample_hold_config (lsample_hold_config),
.stop_sync_channels (stop_sync_channels),

.up_rstn (up_rstn),
.up_clk (up_clk),
Expand Down
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