adrv9009/zc706: Replace dacfifo with data_offload

Signed-off-by: Ionut Podgoreanu <[email protected]>
analogdevicesinc · Nov 11, 2024 · e2a1961 · e2a1961
1 parent f6d0348
commit e2a1961
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Showing 5 changed files with 55 additions and 20 deletions.
diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl
@@ -110,13 +110,13 @@ ad_ip_parameter axi_adrv9009_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST true
 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC true
 
-set data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width]
 ad_data_offload_create $dac_data_offload_name \
                        1 \
-                       0 \
-                       $data_offload_size \
+                       $dac_data_offload_type \
+                       $dac_data_offload_size \
                        $dac_data_width \
-                       $dac_data_width
+                       $dac_data_width \
+                       $dac_axi_data_width
 
 ad_connect $dac_data_offload_name/sync_ext GND
 

diff --git a/projects/adrv9009/zc706/Makefile b/projects/adrv9009/zc706/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -10,11 +10,12 @@ M_DEPS += ../common/adrv9009_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/zc706/zc706_plddr3_dacfifo_bd.tcl
 M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
 M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
 M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
 M_DEPS += ../../../library/util_cdc/sync_bits.v
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/util_pulse_gen.v
 M_DEPS += ../../../library/common/ad_iobuf.v
@@ -32,10 +33,11 @@ LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_rx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
+LIB_DEPS += data_offload
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_cpack2
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr
-LIB_DEPS += xilinx/axi_dacfifo
 LIB_DEPS += xilinx/util_adxcvr
 
 include ../../scripts/project-xilinx.mk
diff --git a/projects/adrv9009/zc706/system_bd.tcl b/projects/adrv9009/zc706/system_bd.tcl
@@ -1,12 +1,13 @@
 ###############################################################################
-## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set dac_fifo_address_width 10
+set dac_data_offload_type 1                      ; ## PL_DDR
+set dac_data_offload_size [expr 1024*1024*1024]  ; ## 1 GB
+set dac_axi_data_width 512
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
 #system ID
@@ -23,7 +24,8 @@ S=$ad_project_params(TX_JESD_S)\
 RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
 L=$ad_project_params(RX_OS_JESD_L)\
 S=$ad_project_params(RX_OS_JESD_S)\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_data_offload_type\
+SIZE=$dac_data_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring
 
@@ -44,6 +46,39 @@ set sys_dma_resetn        [get_bd_nets sys_250m_resetn]
 
 source ../common/adrv9009_bd.tcl
 
+if {$dac_data_offload_type} {
+
+    ad_ip_instance proc_sys_reset axi_rstgen
+    ad_ip_instance mig_7series axi_ddr_cntrl
+    file copy -force $ad_hdl_dir/projects/common/zc706/zc706_plddr3_mig.prj [get_property IP_DIR \
+      [get_ips [get_property CONFIG.Component_Name [get_bd_cells axi_ddr_cntrl]]]]
+    ad_ip_parameter axi_ddr_cntrl CONFIG.XML_INPUT_FILE zc706_plddr3_mig.prj
+
+    # PL-DDR data offload interfaces
+    create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
+    create_bd_port -dir I -type rst sys_rst
+    set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
+    create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
+
+    ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk
+    ad_connect axi_ddr_cntrl/ui_clk $dac_data_offload_name/storage_unit/m_axi_aclk
+    ad_connect axi_ddr_cntrl/S_AXI $dac_data_offload_name/storage_unit/MAXI_0
+    ad_connect axi_rstgen/peripheral_aresetn $dac_data_offload_name/storage_unit/m_axi_aresetn
+    ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn
+    ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in
+
+    assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
+
+    ad_connect  sys_rst axi_ddr_cntrl/sys_rst
+    ad_connect  sys_clk axi_ddr_cntrl/SYS_CLK
+    ad_connect  ddr3    axi_ddr_cntrl/DDR3
+    ad_connect  axi_ddr_cntrl/device_temp_i GND
+    ad_connect  $dac_data_offload_name/i_data_offload/ddr_calib_done axi_ddr_cntrl/init_calib_complete
+
+    ad_ip_parameter $dac_data_offload_name/storage_unit CONFIG.DDR_BASE_ADDDRESS [format "%d" 0x80000000]
+
+}
+
 ad_ip_parameter axi_adrv9009_rx_dma CONFIG.FIFO_SIZE 32
 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.FIFO_SIZE 32
 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.FIFO_SIZE 32

diff --git a/projects/adrv9009/zc706/system_top.v b/projects/adrv9009/zc706/system_top.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -340,7 +340,6 @@ module system_top (
     .dio_p (gpio_bd));
 
   system_wrapper i_system_wrapper (
-    .dac_fifo_bypass (gpio_o[60]),
     .adc_fir_filter_active (gpio_o[61]),
     .dac_fir_filter_active (gpio_o[62]),
     .ddr3_addr (ddr3_addr),

diff --git a/projects/adrv9009/zcu102/system_bd.tcl b/projects/adrv9009/zcu102/system_bd.tcl
@@ -1,15 +1,13 @@
 ###############################################################################
-## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-## FIFO depth is 18Mb - 1M samples
-set dac_fifo_address_width 17
-
-## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
+set dac_data_offload_type 0                   ; ## BRAM
+set dac_data_offload_size [expr 2*1024*1024]  ; ## 2 MB
+set dac_axi_data_width 256
 
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
 #system ID
@@ -26,7 +24,8 @@ S=$ad_project_params(TX_JESD_S)\
 RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
 L=$ad_project_params(RX_OS_JESD_L)\
 S=$ad_project_params(RX_OS_JESD_S)\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_data_offload_type\
+SIZE=$dac_data_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring