i3c_controller: clean-up, add debug parameter

Invert speed grade values order. Remove clk_div module. Add DEBUG_IGNORE_NACK parameter to ignore when a transfer is NACKed, useful for testing without a peripheral on the bus, Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Oct 19, 2023 · 4104f54 · 4104f54
1 parent cc25bbe
commit 4104f54
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Showing 11 changed files with 120 additions and 219 deletions.
diff --git a/docs/regmap/adi_regmap_i3c_controller.txt b/docs/regmap/adi_regmap_i3c_controller.txt
@@ -421,14 +421,14 @@ ENDREG
 FIELD
 [0] 0x??
 OPS_MODE
-WO
+RW
 Set 0 to private transfers, 1 to offload.
 ENDFIELD
 
 FIELD
 [4:1] 0x??
 OPS_OFFLOAD_LENGTH
-WO
+RW
 Offload commands length.
 ENDFIELD
 
@@ -438,10 +438,10 @@ OPS_SPEED_GRADE
 RW
 Sets the speed grade in push-pull mode.
 Speed with 100MHz driver clock are:
-00: 12.50MHz
-01:  6.25MHz
-10:  3.12MHz
-11:  1.56MHz (default)
+00:  1.56MHz (default)
+01:  3.12MHz
+10:  6.25MHz
+11: 12.50MHz
 ENDFIELD
 
 [5] 0x0
@@ -595,6 +595,8 @@ The state can also be overwritten to explicit attach device (e.g. has static add
 A slot cannot be recycled, when the device is detached, it still keeps its slot in
 case it is attached again, effectively, only its IBIs are rejectedin the detached
 state.
+The controller cannot be detached, instead, poll OPS_STATUS_NOP to identify if the
+controller is doing free/not doing any procedure before recondiguring it.
 ENDFIELD
 
 FIELD

diff --git a/library/i3c_controller/i3c_controller_core/Makefile b/library/i3c_controller/i3c_controller_core/Makefile
@@ -8,12 +8,10 @@ LIBRARY_NAME := i3c_controller_core
 
 GENERIC_DEPS += i3c_controller_core.v
 GENERIC_DEPS += i3c_controller_framing.v
-GENERIC_DEPS += i3c_controller_phy_sda.v
 GENERIC_DEPS += i3c_controller_word.v
 GENERIC_DEPS += i3c_controller_word_cmd.v
 GENERIC_DEPS += i3c_controller_bit_mod.v
 GENERIC_DEPS += i3c_controller_bit_mod_cmd.v
-GENERIC_DEPS += i3c_controller_clk_div.v
 
 XILINX_DEPS += i3c_controller_core_constr.ttcl
 XILINX_DEPS += i3c_controller_core_ip.tcl

diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v
@@ -49,10 +49,10 @@ module i3c_controller_bit_mod (
   // Indicates that the bus is not transfering,
   // is different from bus idle because does not wait 200us after Stop.
   output cmd_nop,
-  // 0: 12.50MHz
-  // 1:  6.25MHz
-  // 2:  3.12MHz
-  // 3:  1.56MHz
+  // 0:  1.56MHz
+  // 1:  3.12MHz
+  // 2:  6.25MHz
+  // 3: 12.50MHz
   input [1:0] scl_pp_sg, // SCL Push-pull speed grade
 
   output rx,
@@ -62,8 +62,8 @@ module i3c_controller_bit_mod (
 
   // Bus drive signals
 
-  output reg sdo,
   output scl,
+  output reg sdo,
   input  sdi,
   output t
 );
@@ -75,7 +75,7 @@ module i3c_controller_bit_mod (
   reg sr;
 
   reg scl_high_reg;
-  wire scl_high = count[pp_sg+2];
+  wire scl_high = count[5-pp_sg];
   wire sdo_w;
   wire t_w;
 
@@ -85,7 +85,7 @@ module i3c_controller_bit_mod (
   for (i = 0; i < 4; i = i+1) begin
     assign scl_end_multi[i] = &count[i+2:0];
   end
-  assign scl_end = scl_end_multi[pp_sg];
+  assign scl_end = scl_end_multi[3-pp_sg];
 
   assign cmd_ready = (scl_end | !transfer) & reset_n;
 
@@ -95,12 +95,12 @@ module i3c_controller_bit_mod (
   always @(posedge clk) begin
     if (!reset_n) begin
       cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01};
-      pp_sg <= 2'b11;
+      pp_sg <= 2'b00;
     end else begin
       if (cmd_ready) begin
         if (cmd_valid) begin
           cmd_r <= cmd;
-          pp_sg <= cmd[1] ? scl_pp_sg : 2'b11;
+          pp_sg <= cmd[1] ? scl_pp_sg : 2'b00;
         end else begin
           cmd_r <= {`MOD_BIT_CMD_NOP_, 2'b01};
         end
@@ -138,8 +138,8 @@ module i3c_controller_bit_mod (
   assign rx = rx_raw;
   assign rx_valid = ~scl_high_reg & scl_high;
 
-  assign sdo_w = sm == `MOD_BIT_CMD_START_   ? (scl_high ? ~count[pp_sg+1] : 1'b1) :
-                 sm == `MOD_BIT_CMD_STOP_    ? (scl_high ?  count[pp_sg+1] : 1'b0) :
+  assign sdo_w = sm == `MOD_BIT_CMD_START_   ? (scl_high ? ~count[4-pp_sg] : 1'b1) :
+                 sm == `MOD_BIT_CMD_STOP_    ? (scl_high ?  count[4-pp_sg] : 1'b0) :
                  sm == `MOD_BIT_CMD_WRITE_   ? st[0] :
                  sm == `MOD_BIT_CMD_ACK_SDR_ ? (scl_high ? rx   : 1'b1) :
                  sm == `MOD_BIT_CMD_ACK_IBI_ ? (scl_high ? 1'b1 : 1'b0) :

diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_clk_div.v b/library/i3c_controller/i3c_controller_core/i3c_controller_clk_div.v
diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core.v b/library/i3c_controller/i3c_controller_core/i3c_controller_core.v
@@ -92,8 +92,10 @@ module i3c_controller_core #(
 
   // I3C bus signals
 
-  output scl,
-  inout  sda
+  output i3c_scl,
+  output i3c_sdo,
+  input  i3c_sdi,
+  output i3c_t
 );
   wire clk_out;
   wire [`MOD_BIT_CMD_WIDTH:0] cmd;
@@ -224,17 +226,10 @@ module i3c_controller_core #(
     .rx_raw(rx_raw),
     .rx_valid(rx_valid),
     .cmd_nop(cmd_nop),
-    .scl(scl),
-    .sdi(sdi_bit),
-    .sdo(sdo_bit),
-    .t(t));
-
-  i3c_controller_phy_sda #(
-  ) i_i3c_controller_phy_sda (
-    .sdo(sdo_bit),
-    .sdi(sdi_bit),
-    .t(t),
-    .sda(sda));
+    .scl(i3c_scl),
+    .sdo(i3c_sdo),
+    .sdi(i3c_sdi),
+    .t(i3c_t));
 
   assign ibi = {ibi_da, ibi_mdb};
   assign ibi_valid = ibi_tick;

diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl b/library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl
@@ -7,12 +7,10 @@ set_module_property ELABORATION_CALLBACK p_elaboration
 ad_ip_files i3c_controller_core [list \
   i3c_controller_core.v \
   i3c_controller_framing.v \
-  i3c_controller_phy_sda.v \
   i3c_controller_word.v \
   i3c_controller_word_cmd.v \
   i3c_controller_bit_mod.v \
   i3c_controller_bit_mod_cmd.v \
-  i3c_controller_clk_div.v \
 ]
 
 # parameters

diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl b/library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl
@@ -6,12 +6,10 @@ adi_ip_files i3c_controller_core [list \
 	"i3c_controller_core_constr.ttcl" \
 	"i3c_controller_core.v" \
 	"i3c_controller_framing.v" \
-	"i3c_controller_phy_sda.v" \
 	"i3c_controller_word.v" \
  	"i3c_controller_word_cmd.v" \
 	"i3c_controller_bit_mod.v" \
  	"i3c_controller_bit_mod_cmd.v" \
-	"i3c_controller_clk_div.v" \
 ]
 
 adi_ip_properties_lite i3c_controller_core
@@ -27,8 +25,10 @@ adi_add_bus "i3c" "master" \
 	"analog.com:interface:i3c_controller_rtl:1.0" \
 	"analog.com:interface:i3c_controller:1.0" \
 	{
-		{"scl" "SCL"} \
-		{"sda" "SDA"} \
+		{"i3c_scl" "SCL"} \
+		{"i3c_sdo" "SDO"} \
+		{"i3c_sdi" "SDI"} \
+		{"i3c_t"   "T"} \
 	}
 adi_add_bus_clock "clk" "i3c" "reset_n"
 

diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v b/library/i3c_controller/i3c_controller_core/i3c_controller_phy_sda.v