axi_ad9963: Remove last sample hold control

Set as default the last smple hold plus code optimization changes.
analogdevicesinc · Oct 26, 2023 · 2903e83 · 2903e83
1 parent 3751cfa
commit 2903e83
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Showing 4 changed files with 4 additions and 42 deletions.
diff --git a/library/axi_ad9963/axi_ad9963.v b/library/axi_ad9963/axi_ad9963.v
@@ -107,8 +107,6 @@ module axi_ad9963 #(
   input           dma_valid_q,
   input           dac_dunf,
 
-  input           hold_last_sample,
-
   // axi interface
 
   input           s_axi_aclk,
@@ -169,8 +167,6 @@ module axi_ad9963 #(
   wire            up_rack_tx_s;
   wire            up_adc_ce;
   wire            up_dac_ce;
-  wire            valid_out_q_s;
-  wire            valid_out_i_s;
 
   // signal name changes
 
@@ -208,10 +204,7 @@ module axi_ad9963 #(
     .adc_status (adc_status_s),
     .up_adc_ce(up_adc_ce),
     .dac_data (dac_data_s),
-    .out_valid_q (valid_out_q_s),
-    .out_valid_i (valid_out_i_s),
     .up_dac_ce(up_dac_ce),
-    .tx_sample_hold (hold_last_sample),
     .up_clk (up_clk),
     .up_adc_dld (up_adc_dld_s),
     .up_adc_dwdata (up_adc_dwdata_s),
@@ -288,12 +281,10 @@ module axi_ad9963 #(
     .dac_valid_i (dac_valid_i),
     .dac_data_i (dac_data_i),
     .dma_valid_i (dma_valid_i),
-    .out_valid_i (valid_out_i_s),
     .dac_enable_q (dac_enable_q),
     .dac_valid_q (dac_valid_q),
     .dac_data_q (dac_data_q),
     .dma_valid_q (dma_valid_q),
-    .out_valid_q (valid_out_q_s),
     .dac_dunf(dac_dunf),
     .up_dac_ce(up_dac_ce),
     .up_rstn (up_rstn),

diff --git a/library/axi_ad9963/axi_ad9963_if.v b/library/axi_ad9963/axi_ad9963_if.v
@@ -73,11 +73,8 @@ module axi_ad9963_if #(
 
   // transmit data path interface
 
-  input               out_valid_q,
-  input               out_valid_i,
   input       [23:0]  dac_data,
   input               up_dac_ce,
-  input               tx_sample_hold,
 
   // delay interface
 
@@ -93,16 +90,15 @@ module axi_ad9963_if #(
   // internal registers
 
   reg     [11:0]  rx_data_p = 0;
-  reg     [11:0]  tx_data_p = 'd0;
-  reg     [11:0]  tx_data_n = 'd0;
-  reg     [23:0]  constant_sample = 'd0;
 
   // internal signals
 
   wire    [11:0]  rx_data_p_s;
   wire    [11:0]  rx_data_n_s;
   wire            rx_iq_p_s;
   wire            rx_iq_n_s;
+  wire    [11:0]  tx_data_p;
+  wire    [11:0]  tx_data_n;
 
   wire            div_clk;
 
@@ -119,26 +115,8 @@ module axi_ad9963_if #(
     end
   end
 
-  always @(posedge dac_clk) begin
-    if (dac_rst == 1'b1) begin
-        tx_data_p <= 24'd0;
-        tx_data_n <= 24'd0;
-        constant_sample <= 24'd0;
-    end else begin
-      if(out_valid_i == 1'b1) begin
-        tx_data_p <= dac_data[11: 0];
-        constant_sample[11: 0] <= tx_sample_hold ? dac_data[11: 0] : 12'd0;
-      end else begin
-        tx_data_p <= constant_sample[11:0] ;
-      end
-      if(out_valid_q == 1'b1) begin
-        tx_data_n <= dac_data[23:12];
-        constant_sample[23:12] <= tx_sample_hold ? dac_data[23:12] : 12'd0;
-      end else begin
-        tx_data_n <= constant_sample[23:12];
-      end
-    end
-  end
+  assign tx_data_p = dac_data[11: 0];
+  assign tx_data_n = dac_data[23:12];
 
   always @(posedge adc_clk) begin
     if (adc_rst == 1'b1) begin

diff --git a/library/axi_ad9963/axi_ad9963_tx.v b/library/axi_ad9963/axi_ad9963_tx.v
@@ -68,12 +68,10 @@ module axi_ad9963_tx #(
   output reg          dac_valid_i,
   input       [15:0]  dac_data_i,
   input               dma_valid_i,
-  output              out_valid_i,
   output              dac_enable_q,
   output reg          dac_valid_q,
   input       [15:0]  dac_data_q,
   input               dma_valid_q,
-  output              out_valid_q,
   input               dac_dunf,
 
   output              up_dac_ce,
@@ -147,7 +145,6 @@ module axi_ad9963_tx #(
     .dac_data_sync (dac_data_sync_s),
     .dac_dds_format (dac_dds_format_s),
     .dma_valid (dma_valid_i),
-    .out_data_valid (out_valid_i),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq),
@@ -181,7 +178,6 @@ module axi_ad9963_tx #(
     .dac_data_sync (dac_data_sync_s),
     .dac_dds_format (dac_dds_format_s),
     .dma_valid (dma_valid_q),
-    .out_data_valid (out_valid_q),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq),

diff --git a/library/axi_ad9963/axi_ad9963_tx_channel.v b/library/axi_ad9963/axi_ad9963_tx_channel.v
@@ -58,7 +58,6 @@ module axi_ad9963_tx_channel #(
   output reg  [11:0]  dac_data_out,
   input       [11:0]  dac_data_in,
   input               dma_valid,
-  output              out_data_valid,
 
   // processor interface
 
@@ -113,8 +112,6 @@ module axi_ad9963_tx_channel #(
   wire    [15:0]  dac_iqcor_coeff_1_s;
   wire    [15:0]  dac_iqcor_coeff_2_s;
 
-  assign out_data_valid = dac_iqcor_valid_s;
-
   // dac iq correction
 
   always @(posedge dac_clk) begin