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AD9371: Fix reset signaling for custom IP Core #129

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AD9371: Fix reset signaling for custom IP Core #129

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3 changes: 2 additions & 1 deletion CI/scripts/matlab_processors.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -446,12 +446,13 @@ proc preprocess_bd {project carrier rxtx} {
# Add 1 extra AXI master ports to the interconnect
set_property -dict [list CONFIG.NUM_MI {22}] [get_bd_cells axi_cpu_interconnect]
#connect_bd_net -net [get_bd_nets axi_adrv9009_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M13_ACLK] [get_bd_pins axi_adrv9009_rx_clkgen/clk_0]
connect_bd_net [get_bd_pins sys_rstgen/interconnect_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN]

if {$rxtx == "rx" || $rxtx == "rxtx"} {
connect_bd_net [get_bd_pins ad9371_rx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN]
connect_bd_net -net [get_bd_nets axi_ad9371_rx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_rx_clkgen/clk_0]
}
if {$rxtx == "tx"} {
connect_bd_net [get_bd_pins ad9371_tx_device_clk_rstgen/peripheral_aresetn] [get_bd_pins axi_cpu_interconnect/M21_ARESETN]
connect_bd_net -net [get_bd_nets axi_ad9371_tx_clkgen] [get_bd_pins axi_cpu_interconnect/M21_ACLK] [get_bd_pins axi_ad9371_tx_clkgen/clk_0]
}
}
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6 changes: 3 additions & 3 deletions hdl/vendor/AnalogDevices/+AnalogDevices/add_clocks.m
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Original file line number Diff line number Diff line change
Expand Up @@ -66,15 +66,15 @@ function add_clocks(hRD,project,design)
case 'RX'
hRD.addClockInterface( ...
'ClockConnection', 'axi_ad9371_rx_clkgen/clk_0', ...
'ResetConnection', 'sys_rstgen/peripheral_aresetn');
'ResetConnection', 'ad9371_rx_device_clk_rstgen/peripheral_aresetn');
case 'TX'
hRD.addClockInterface( ...
'ClockConnection', 'axi_ad9371_tx_clkgen/clk_0', ...
'ResetConnection', 'sys_rstgen/peripheral_aresetn');
'ResetConnection', 'ad9371_tx_device_clk_rstgen/peripheral_aresetn');
case 'RX & TX'
hRD.addClockInterface( ...
'ClockConnection', 'axi_ad9371_rx_clkgen/clk_0', ...
'ResetConnection', 'sys_rstgen/peripheral_aresetn');
'ResetConnection', 'ad9371_rx_device_clk_rstgen/peripheral_aresetn');
% case 'OBS'
% hRD.addClockInterface( ...
% 'ClockConnection', 'axi_adrv9371_rx_os_clkgen/clk_0', ...
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