axi_dma_wr does not respect TKEEP

[KireinaHoro]

I have a input stream to the AXI DMA with "holes" (i.e. tkeep[...] = 0). Per AXIS specification, these bytes should be discarded. However, the DMA module does not behave as such:

I have tried with ENABLE_UNALIGNED to 0 or 1. Is this use case not supported, or am I misunderstanding something? Thanks!

[KireinaHoro]

Alternatively there is an AXIS packer module from ZipCPU, but I'm still wondering if the AXI DMA module would support it natively, or maybe there could be a module in the verilog-axis repo.