As a part of my minor project, I implemented the Advanced Encryption Standard (AES) on a Xilinx Artix-7 xc7a200tfbg676-2 FPGA. Vivado High Level Synthesis (HLS) tool converted the C code to RTL design. Various optimization techniques were used like:
- Unrolling Loops
- Pipelining
- Reducing loop iterations
After various levels of optimization, we got a high frequency (244 MHz) and throughput (30.48 Gpbs). The optimized implementation also consumes lower BRAMs and area.
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