synth_quicklogic: add -noflatten option #4735
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What are the reasons/motivation for this change?
Not flattening gives faster execution time and lower memory usage in exchange for worse QoR. Probably more useful for debugging/exploring synthesis results than for actual use with an FPGA (not sure if the VPR P&R flow even accepts hierarchical netlists at all).
Explain how this is achieved.
Same way as for the other
synth_*passes (exceptsynth_xilinxwhich doesn't flatten by default).If applicable, please suggest to reviewers how they can test the change.