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frontend: Fixes verific import around range order #4379

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merged 3 commits into from
May 9, 2024
Merged

frontend: Fixes verific import around range order #4379

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a2c1b26
frontend: Fixes verific import around range order
QuantamHD May 8, 2024
c039da2
renames variables for more code clairty
QuantamHD May 8, 2024
82a4a87
Fixes error with vector indicies of the form [2:7] [-12:7]
QuantamHD May 8, 2024
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12 changes: 10 additions & 2 deletions frontends/verific/verific.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2156,8 +2156,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
int port_offset = 0;
if (pr->GetPort()->Bus()) {
port_name = pr->GetPort()->Bus()->Name();
port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
int msb_index = pr->GetPort()->Bus()->LeftIndex();
int lsb_index = pr->GetPort()->Bus()->RightIndex();
int index_of_port = pr->GetPort()->Bus()->IndexOf(pr->GetPort());
port_offset = index_of_port - min(msb_index, lsb_index);
// In cases where the msb order is flipped we need to make sure
// that the indicies match LSB = 0 order to match the std::vector
// to SigSpec LSB = 0 precondition.
if (lsb_index > msb_index) {
port_offset = abs(port_offset - lsb_index);
}
}
IdString port_name_id = RTLIL::escape_id(port_name);
auto &sigvec = cell_port_conns[port_name_id];
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