Docs: Less exaggeration

README.md

@@ -264,8 +264,8 @@ Additional information
 ======================
 
 The ``read_verilog`` command, used by default when calling ``read`` with Verilog
-source input, does not perform any syntax checking.  You should instead lint
-your source with another tool such as
+source input, does not perform syntax checking.  You should instead lint your
+source with another tool such as
 [Verilator](https://www.veripool.org/verilator/) first, e.g. by calling
 ``verilator --lint-only``.