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Multi-core synchronization instructions (XTheadSync)

Frozen
 The XTheadSync extension is stable.

The XTheadSync ISA extension provides multi-core synchronization instructions.

Extension version: 1.0.

The table below gives an overview of the instructions:

RV32 RV64 Mnemonic Instruction

Y

Y

th.sfence.vmas rs1, rs2

[xtheadsync-insns-sfence-vmas]

Y

Y

th.sync

[xtheadsync-insns-sync]

Y

Y

th.sync.s

[xtheadsync-insns-sync-s]

Y

Y

th.sync.i

[xtheadsync-insns-sync-i]

Y

Y

th.sync.is

[xtheadsync-insns-sync-is]

Availability

The XTheadSync extension’s availability can be probed via the th.sxstatus.THEADISAEE bit (bit 22). The XTheadSync extension is available if and only if this bit is 1. Refer to [xtheadsxstatus] for more information about the th.sxstatus CSR.