- Synopsis
-
Ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction.
- Mnemonic
-
th.sync
- Encoding
{reg:[
{ bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] },
{ bits: 5, name: 0x0 },
{ bits: 3, name: 0x0, attr: ['CMO'] },
{ bits: 5, name: 0x0 },
{ bits: 5, name: 0x18, attr: ['SYNC'] },
{ bits: 7, name: 0x00 },
]}
- Description
-
This instruction ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction. It is stricter than standard RISC-V fence instruction. Fence only influences the order of load/store instructions while th.sync influences all the instructions, including all explicit memory accesses and cache operations.
- Operation
out_of_order_barrier()- Permission
-
This instruction can be executed in all privilege levels.
- Exceptions
-
This instruction does not trigger any exceptions.
- Included in
| Extension |
|---|
XTheadSync ([xtheasync]) |