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Welcome to the FORCE-RISCV wiki!

What is FORCE-RISCV?

FORCE-RISCV is an open-source RISCV Instruction Stream Generator (ISG), a powerful verification tool for RISC-V based CPU design, developed and released by IC-Lab of Futurewei Technologies, contributed to the OpenHW Group under Apache 2.0 license.

The FORCE-RISCV Instruction Stream Generator (ISG)：

• Supports 64-bit version of RISC-V with RV64I, M, A, Zicsr, F, D, C extensions, Machine, Supervisor, User modes.
• Supports dynamic ISS interaction, dynamic Virtual Memory management, loops, configurable state transition.
• It has powerful and extensible Python scriptable API based test template writing framework.
• Supports Vector extension V0.9.
• Supports full paging exception control.
• Future release will include but not limited to advanced memory sub-system verification features, advanced resource dependency, and 32-bit version of RISC-V.

Getting Started

FORCE-RISCV is available for download at https://github.com/openhwgroup/force-riscv

Simply download and start using. Following is a sample bash script to download and compile the tool:

#!/bin/bash

####################
# Download the force-riscv source
####################
git clone https://github.com/openhwgroup/force-riscv

####################
# Build the force-riscv executable
####################
export FORCE_CC=/usr/bin/g++
export FORCE_PYTHON_VER=3.6
export FORCE_PYTHON_LIB=/usr/lib/x86_64-linux-gnu/
export FORCE_PYTHON_INC=/usr/include/python3.6
source setenv.bash

cd force-riscv
make |& tee make.log
make tests |& tee make_tests.log

####################
# Run examples test generation
####################
fpath=`pwd`
export FORCE_PATH=${fpath}

# Run example rv64 test generation
cd ..
mkdir tests_rv64
cd tests_rv64
$FORCE_PATH/utils/regression/master_run.py -f $FORCE_PATH/tests/riscv/_def_fctrl.py -c $FORCE_PATH/utils/regression/config/_riscv_rv64_fcfg.py -k all

# Run example rv32 test generation
cd ..
mkdir tests_rv32
cd tests_rv32
$FORCE_PATH/utils/regression/master_run.py -f $FORCE_PATH/tests/riscv/_rv32_fctrl.py -c $FORCE_PATH/utils/regression/config/_riscv_rv32_fcfg.py -k all

Welcome to join openhw FORCE-RISCV VTG to track further developement of FORCE-RISCV

Follow the steps to reigister eclipse account: https://www.openhwgroup.org/register/

Then join FORCE-RISCV VTG mattermost, which is openhw's official instant message communication tool: https://mattermost.openhwgroup.org/all-users/channels/vtg-force-riscv#

Stage2 development of FORCE-RISCV will be tracked in FORCE-RISCV VTG mattermost. Welcome to join.